Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

• Transistor-level , SPICE
• Interconnect parasitics, SPEF
• Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out how everything is connected. IP reuse is here to stay, yet the challenge with using hundreds of IP blocks is finding out how they are all connected and to ensure consistency of signal naming conventions, and making sure that no pins are un-connected or misconnected. The debug process alone is time consuming and tedious, especially if you don’t have a specialized tool designed for the task.

Fortunately there is hope, because Concept Engineering has been in the forefront of providing engineers with a visualizing and debugging tool called StarVision Pro. There’s a webinar scheduled for Thursday, September 12th at 10AM PDT that will help engineers debug quicker by:

• VISUALIZE: Render schematics on the fly for VHDL/Verilog/Spice level netlists to understand the function of design easily.
• PRUNE: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists for reuse as IP or external use in partial simulation
• CLOCK DOMAIN ANALYZER: Visualize and detect different clock domains in the design.
• CROSS-PROBE: Drag & drop selected components/nets between all design views to cross probe and shorten debug time, especially during tape-out for full-chip debug. Also the ability to cross-probe analog and digital simulation data on the netlist.
• PARASITIC: Visualize and analyze parasitic networks and create SPICE netlists for critical path simulation.
• NETLIST REDUCTION: Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function
• SKILL EXPORT: Export schematics and schematic fragments into Cadence Virtuoso.
• SOC OR MIXED SIGNAL DESIGN: Visualize, Debug and Analyze the RTL, GATE, and SPICE Design in one cockpit!
• DOCUMENT: Generate design statistics & reports: Instance & primitive counts
• TCL API: Extend the functionality of StarVision to match project needs by interfacing with the open database through TCL scripts and in batch mode
• IDENTIFY DIFFERENCES IN SCHEMATICS: Extend the capabilities of the tool to identify differences between designs.

At my last EDA company we used StarVision Pro to inspect SPICE netlists with extracted parasitics in order to understand connectivity and debug circuit simulation results, and this tool saved us hours of effort versus manually tracing and creating a schematic from a netlist. Why worker harder when you can work smarter?

Register online here.

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