Merchant microcontrollers are usually made available in a wide range of variants based on one architecture with different peripheral payloads and packaging options. A couple of companies, notably Cypress with their PSoC families and Silicon Labs with the EFM8 Laser Bee, have tried configurable logic in an attempt to solve the variant challenge.
A more flexible option would be to use a Flex Logix EFLX-100 core to deliver the configurability. This would give MCU manufacturers (or IoT chip manufacturers) the ability to design one die which could hit several application spots easily. Ultimately, configurability might be passed through to OEM customers with the right design tools – something Flex Logix is thinking through currently. For the time being, let’s look at the key technical items that need to be considered to take a fixed MCU toward a more configurable solution with EFLX-100 cores in the mix.
Years ago, ARM standardized its efforts on AMBA to make it easier for both its chip customers and ecosystem partners to deliver IP that works together. When the Cortex-M families were introduced, they came with AMBA, and particularly the Advanced Peripheral Bus (APB) for simpler, lower throughput implementations. EFLX-100 cores are not hard coded to any specific interface bus. Since AMBA signaling uses defined input and output lines, it is a simple matter to interface the EFLX-100 directly onto an APB. In block diagram form:
Taking a closer look at the signaling requirements, an APB slave interface needs 102 pins, with 69 inputs and 33 outputs. This can be handled in a single EFLX-100 core, taking only 2 logic RBBs and 7 LUTs. The remainder of the EFLX-100 array can then in turn be programmed with I/O mapping to handle a range of options. Additionally, to support sleep functionality, the EFLX-100 can be power gated and isolated from the APB slave interface.
Flex Logix has studied some typical peripherals to see how implementations might go. One EFLX-100 core easily handles a simple UART with no FIFOs or flow control. Two cores handle a 32-port GPIO configuration with completely soft I/O pins. Four cores handle a full 16550 serial communication controller. Perhaps more importantly: by laying down an array of four EFLX-100 cores, all of these configurations are possible in a single, reconfigurable device.
The complete Flex Logix application note is available online, no registration required:
Reconfiguring low-speed I/O doesn’t sound all that glamorous at first blush. The world of the MCU is very different from the world of the highly optimized application SoC. We’ve come from the direction of using the DSP capability of the EFLX cores as one of the compelling arguments in their use with previous posts. However, costs per mask start are accelerating, even for relatively low complexity MCUs.
If a rethink of using programmable logic in a single, configurable part manages to eliminate even a couple of mask starts, the strategy pays for itself quickly. As those of you who follow me know, I see the domain of the merchant MCU starting to change into a more customized part designed and optimized for IoT missions. I don’t believe for one second IoT chips will be driven to that 2-cent level; this hasn’t happened for merchant MCUs so far, because no merchant company can afford to ship each chip with a quarter or even a half dollar taped to it.
I can see companies doing IoT chips really benefitting here. Rather than trying to serve too many masters with dozens of configurations, one IoT chip could be crafted using Flex Logix technology to very specifically serve a few roles, perhaps countable using fingers on only one or two hands.