Creating a better embedded FPGA IP product

Our introduction to Flex Logix and its embedded FPGA core IP drew several comments, predominantly along the lines of a few things like this have been tried before. In this installment, we dive into the EFLX cores, the FPGA toolchain, the roadmap, and a powerful integration feature.

While Flex Logix is quick to point out they are not competing with FPGA companies, tearing open an EFLX core reveals similar primitive blocks. There are MACs and adders, LUTs and RAM controllers, reconfigurable FFs, and I/O blocks. The basic idea is a sea of logic in a scalable interconnect fabric ringed by hundreds to thousands of I/O pins.

The fabric is the key to both performance and scalability. Flex Logix claims that for a given number of LUTs, their EFLX Network delivers more density – as much as 45% smaller compared to the traditional mesh network in FPGAs. Add to that how individual EFLX core tiles can be snapped together to form MxN arrays using the same EFLX Network for interconnect, and the power of the concept starts to become clear.

That’s about where our readers jumped in on embedded FPGA IP history. There were a couple of tries by Actel (thanks to Sam Beal for pointing that out), most notably the VariCore environment they acquired in buying ProSys. There were attempts at Agere Systems and LSI Logic via Adaptive Silicon. There was a product from m2000, and even an open source effort called GOSPL from STMicro. None enjoyed rousing success, and it boiled down to two issues.

One issue would be trying to compete with Xilinx, especially since they have moved into the all-programmable SoC business with ARM cores on chip. However, in terms of cost and power consumption, that is a relatively expensive approach compared to an SoC design with point reconfigurability. Flex Logix has made a good strategic decision to differentiate, enabling their customers to do what they do best: customize and optimize.

I’ll let a reader comment summarize the other potential stumbling block:

The big issue is not the IP but the toolchains ….

All those prior FPGA IP attempts used a proprietary toolchain in one form or another, eventually spitting out a library cell or netlist that integrated into an ASIC-like flow. There was little opportunity to optimize interconnect or scale; mostly they were just a blob of programmable logic.

A lot of people just go with the flow, especially when it comes to Xilinx FPGAs and tools. We’re big fans of Xilinx Vivado as well, and it relentlessly improves in every successive release. However, there are other high-performance FPGA synthesis tools out there keeping pace: Synopsys Synplify (Premier and Pro) and Mentor Graphics Precision Synthesis. This is where Flex Logix has been really smart in not reinventing the wheel, leveraging their efforts with front end synthesis tools already in wide circulation and using those outputs to target the EFLX array using the EFLX Compiler.

Each EFLX core is divided into Reconfigurable Building Blocks (RBBs) tuned for existing synthesis tools. This allows highly optimized interconnect and logic placement. Any RBB can connect with any other RBB, on the same EFLX tile or another tile in a connected EFLX array, up to a practical limit of a 7×7 array size. Using commercial synthesis toolchains also enables use of their other features including synthesis constraints and FPGA debug tools.

We discussed the EFLX-2.5K core last time. There are two other directions on the roadmap, one larger, one smaller. The EFLX-100 core is the ultimate in point-level reconfigurability where just a few gates are needed, and Flex Logix has targeted it for a mature TSMC 40nm LP/ULP process. The technology is scalable, so for larger designs a larger EFLX core could easily be developed to support array configurations over 300K gates.

One other point about EFLX arrays could really help system-level SoC architecture. Since the EFLX core tiles are independent, they can be spaced apart, leaving room for external RAM integration between tiles. Since many FPGA configurations run head on into block RAM resource limitations, this is a great idea. External RAM is mapped and compiled onto the array. Tiles with DSP emphasis or logic emphasis can be mixed and matched in an array for optimization.

In the next few weeks, Flex Logix is hitting the road in the TSMC 2016 Technology Symposium, coming to San Jose, Boston, and Austin – be sure to catch their exhibit at those events.

Our introductory blog post on Flex Logix, for reference:
Reconfigurable redefined with embedded FPGA core IP