Integrated 2D NoC vs a Soft Implemented 2D NoC

We are living in the age of big data and the future is going to be even more data centric. Today’s major market drivers all have one thing in common: efficient management of data. Whether it is 5G, hyperscale computing, artificial intelligence, autonomous vehicles, or IoT, there is data creation, processing, transmission, and storage all around us. All of these aspects of data management need to happen very fast.  Data center operators cannot afford to tolerate data traffic jams anywhere in the data path. They need to process incoming data efficiently and move the data to its destination rapidly. The underlying system hardware architecture design is a critical factor in allowing rapid data transfer.  Therefore, the selecting of the right processing architecture will have a major impact on performance.

SemiWiki has covered the Achronix Speedster7t FPGA devices and their various features in several posts because of their innovative 2D NoC features.  For rapidly moving data throughout a chip, there is little contention that a Network-on-Chip (NoC) is an excellent approach. A NoC architecture is better at moving data than a conventional bus architecture and a crossbar architecture. But should you implement your own 2D NoC on an FPGA fabric or leverage a pre-built 2D NoC? Is one 2D NoC implementation better than another? This is the question that Achronix answers in a recently published whitepaper titled “The Achronix Integrated 2D NoC Enables High-Bandwidth Designs.” Of course, the comparison study is between Achronix’s own 2D NoC and a soft implemented 2D NoC on their Speedster7t family of FPGAs. This post is a synthesis of what I gathered from the whitepaper.

The Contender 2D-NoC

The soft 2D NoC chosen for the comparison project is from Milan Polytechnic (https://github.com/agalimberti/NoCRouter, 2017) based on peer reviews and ease of portability to an FPGA fabric. It implements a wormhole lookahead predictive switching in a unidirectional mesh.

Benchmark Design

To quantify the differences between the Speedster7t 2D NoC and the soft implementation using FPGA fabric resources, a two dimensional convolution (Conv2d) design was created. This design performs AlexNet 2D convolution on an input image and contains 19 instances the Conv2d design.

The Metrics Used for Comparison

The metrics that are picked for comparison of any two solutions should be relevant and important to the solutions’ users. In the context of what is being compared, the following metrics were chosen:

• How many resources are needed for each of the two solutions?
• What is the performance of the design using each solution?
• How long does it take to design and compile the design?

Results from Achronix’s 2D NoC Comparison Study

Performance

The use of the integrated 2D NoC produces an elegant, repeatable structure to place and route the design that results in regular routing with less congestion. Refer to Figure below. Using the Achronix’s integrated 2D NoC achieves a maximum frequency of 565MHz for the Conv2d design.

Routing of the Conv2 Design Using the Achronix Integrated 2D NoC

Compare the above with the complex, irregular and congested routing when using the soft implemented 2D NoC. Refer to Figure below. Timing is also compromised as deep LUT logic is needed to select the appropriate paths in the soft implemented 2D NoC.

Routing of the Conv2d Design Using the Soft Implemented 2D NoC

Design and Compile Time

The full-featured implementation of the Achronix integrated 2D NoC eliminates a large amount of design work for the users. For example, built-in features such as clock-domain crossing logic, transaction flow control, and decoding of addresses. This allows designers to concentrate just on the value added user logic connecting to the 2D NoC. Along with reduced design time, a design that utilizes the Achronix integrated 2D NoC uses fewer resources than one that uses a soft implemented 2D NoC. The result is less logic to place and route, and results in faster compile time through the tools.

Summary

The Speedster7t architecture significantly improves design productivity while making the Achronix FPGAs very effective for high-bandwidth applications. The designs benefit from reduced logic utilization, reduced memory requirements and increased performance. You can download the whitepaper here. Refer to the table below for the results from the comparative study.

Conv2d Design and Comparison of the 2D NoCs

Also read:

2D NoC Based FPGAs Valuable for SmartNIC Implementation

Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC

Take the Achronix Speedster7t FPGA for a Test Drive in the Lab