Achronix is known for its high-performance FPGA solutions. In this post, I’ll explore the Speedster7T FPGA. This FPGA family is optimized for high-bandwidth workloads and eliminates performance bottlenecks with an innovative architecture. Built on TSMC’s 7nm FinFET process, the family delivers ASIC-level performance while retaining the full programmability of an FPGA. There is a lot to learn about the Speedster7T. Achronix now has a video available that will answer a lot of those questions. There is a link to that video and more coming, but first let’s see what happens when you take the Achronix Speedster7t FPGA for a test drive in the lab.
Steve Mensor, VP of sales and marketing at Achronix introduces the video. Steve has been with Achronix for almost ten years and spent 21 years at Altera before that. He certainly knows a lot about FPGAs – design and application. Steve begins by outlining some of the elements of the previously mentioned innovative architecture. There is a lot of dedicated capability on board the Speedster7T. This includes:
- 112 Gbps SerDes
- 400G Ethernet
- PCIe Gen5
- GDDR6 running at 4 Tbps
- DDR 4 running at 3,200 Mbps
- A proprietary machine learning processor
- 2D network on chip (NoC)
The proprietary machine learning processor delivers a lot of functionality, including floating point, block floating point and integer operations. The 2D NoC is a new-to-the-industry capability for FPGAs from Achronix. The NoC can route data from any of the high-speed interfaces to the core FPGA fabric at 2 GHz without consuming any of the FPGA logic resources. All of this on-board technology allows you to get to ASIC-level performance in an FPGA.
Steve then hands the presentation over to Katie Purcell, application engineering manager at Achronix. Katie has been with Achronix for four years. Prior to that she was an ASIC designer. She also spent time at Xilinx. Katie is the one who takes the Speedster7t FPGA for a test drive in the lab, and she is definitely up to the challenge.
Katie takes the viewer into the Achronix lab where bring-up of the Speedster7T is being performed – validation and characterization. The demo Katie presents shows the device running 400G ethernet traffic on the Achronix VectorPath accelerator card. Katie begins by summarizing the key elements of the demonstration, which include:
- 8 X 50G external interface
- Single 400G interface in ethernet subsystem
- Data divided to four separate streams in the 2D NoC
- Each stream processed independently
Katie spends some time on the 2D NoC. She points out that this capability makes the design simpler and easier to close timing. This unique 2D NoC came up several times during the demo. It’s worth digging in a bit more to understand it. Achronix previously presented a webinar about this unique capability that was covered on SemiWiki called 5 Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC. The good news is that a replay of this very informative webinar is now available. You can watch it here.
Katie takes you through a detailed look at what’s going on inside the Speedster7T device as it processes the data packets. Knowing those details helps to understand the ease of setup and delivered accuracy that is shown during the demo. If you think a unique device like this could help your design project, I highly recommend you watch the demo. It’s short, but very useful. You can access the demo video here.
Now you know how to take the Achronix Speedster7t FPGA for a test drive in the lab. You can find out more details about this unique FPGA family here.Share this post via: