WP_Term Object
(
    [term_id] => 37
    [name] => Achronix
    [slug] => achronix
    [term_group] => 0
    [term_taxonomy_id] => 37
    [taxonomy] => category
    [description] => 
    [parent] => 36
    [count] => 49
    [filter] => raw
    [cat_ID] => 37
    [category_count] => 49
    [category_description] => 
    [cat_name] => Achronix
    [category_nicename] => achronix
    [category_parent] => 36
)
            
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WP_Term Object
(
    [term_id] => 37
    [name] => Achronix
    [slug] => achronix
    [term_group] => 0
    [term_taxonomy_id] => 37
    [taxonomy] => category
    [description] => 
    [parent] => 36
    [count] => 49
    [filter] => raw
    [cat_ID] => 37
    [category_count] => 49
    [category_description] => 
    [cat_name] => Achronix
    [category_nicename] => achronix
    [category_parent] => 36
)

PCIe Gen5 Interface Demo Running on a Speedster7t FPGA

PCIe Gen5 Interface Demo Running on a Speedster7t FPGA
by Kalar Rajendiran on 11-24-2021 at 10:00 am

The major market drivers of today all have one thing in common and that is the efficient management of data. Whether it is 5G, hyperscale computing, artificial intelligence, autonomous vehicles or IoT, there is data creation, processing, transmission and storage. All of these aspects of data management need to happen very fast. Fast storage and high-speed networking are ever more critical for today’s applications. Data centers and hyperscale data centers cannot afford to tolerate data traffic jams anywhere in the data path. They need to process incoming external data very efficiently and get the data to the final destination rapidly. But, with Ethernet speeds evolving must faster than PCIe generational speed jumps, the gap is growing.

As network interfaces upgrade from 100GbE to 400GbE, a full-duplex 400GbE link would require 800Gbps of bandwidth that translates to 100GB/s. A PCIe Gen4 x16 cannot handle that bandwidth but a PCIe Gen5 x16 can. And, as offloading tasks that were traditionally handled by the host is becoming more common, NVMe storage is being used like network attached storage with access managed by a SmartNIC. A faster NVMe storage solution can be implemented with PCIe Gen5. In other words, PCIe Gen5 will become very important for data centers where fast storage and high-speed networking are critical for communications.

SmartNICs are being expected to handle more functionality and offer flexibility to handle changing data management requirements. An earlier blog discussed how a reconfigurable SmartNIC can benefit from a Speedster7t FPGA based implementation. The focus of that post was the 2D-NoC feature of the Speedster7t FPGA. The blog was based on an Achronix webinar titled “Five Reasons Why a High Performance Reconfigurable SmartNIC Demands a 2D NoC.“ You can watch that on-demand webinar by registering here.

This blog focuses on the Speedster7t FPGA’s PCIe Gen5 capability. The Speedster7t family is one of the first FPGAs available now that natively supports the PCIe Gen5 specification. It is in this context that a recent video publication by Achronix is of interest. The video shows a demonstration of a successful PCIe Gen5 link between a Teledyne LeCroy PCIe exerciser and a Speedster7t FPGA. Teledyne LeCroy offers an integrated and automated compliance testing system, approved by the PCI-SIG® as a standard tool for compliance testing of PCIe specifications. The PCI Express exerciser can generate PCI Express transactions, observe behavior, and perform both stress testing and compliance testing.

Steve Mensor, vice president of sales and marketing at Achronix introduces the Speedster7t FPGA with a high-level overview of its features. He then hands off to Katie Purcell, application engineering manager at Achronix to present the PCIe Gen5 interface demo on Speedster7t FPGA. The demo setup includes a Speedster7t FPGA board, the PCIe exerciser and a connected computer to set up the exerciser.

PCIe Gen5 Interface Demo Board

First, Katie launches the exerciser’s control program graphical user interface (GUI) on the connected computer. The goal of the demo is to show the FPGA successfully link (achieving PCIe L0 state) at Gen1 through Gen5 specs. The demo shows that a PCIe L0 state can be achieved between the FPGA and the Gen5 capable LeCroy A58 PCIe exerciser. Although the FPGA can support up to PCIe Gen5 x16, the demo is run in x8 mode as that is the maximum mode supported by the exerciser. The demo shows all eight lanes downstream and upstream show the status of having reached the L0 state for a 32GT/s PCIe Gen5 data rate. The exerciser is cycled through to show that links can be achieved at all 5 PCIe Gen speeds.

PCIe Gen5 x8 Link Up Successful

If you are involved in or will be upgrading to a PCIe Gen5 system, you may want to watch the demo. It runs just 4-minutes long but could be useful for your project. You can find out more details about the Speedster7t FPGA family here.

 

 

 

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