IC Layout Design at Qualcomm

I first met Betty Pokerwinski of Qualcomm at LinkedIn in the group called IC Layout Designers. I post frequently on LinkedIn and a blog article on an EDA tool called Visual Design Diff from ClioSoft created quite a discussion, enough so that I contacted Betty to learn more about her IC layout group at Qualcomm.

Questions and Answers

Q: How long have you been at Qualcomm?
A: Since 2003

Q: What types of chips does your group work on?
A: MSMs, CSM, APQ, are 90% of the work we contribute to.

Q: What are the end markets for your chips (cellphones, tablets, etc.)?
A: Mostly Cellphones but there are other products in our future.

Q: How many chips a year are you responsible for?
A: We are not responsible for the ‘chip’ level work. We provide the internal IPs of the chips listed above as noted in LinkedIn.

Q: What is the complexity of the chips in transistor count?
A: They are SOCs and quite complex.

Q: What does your IC design flow look like?
A: Mainly IP and of course includes DRC, LVS, Softcheck, LEF and sometimes DEF generations. Cadence tools for IC layout.

Q: What part does data management play in your IC design flow?
A: A very large part. Ever project is managed by Synchronicity DM.

Q: Which ClioSoft tools are you using?
A: VDD only.

Q: How does the VDD tool help your project?
A: This tool is quite remarkable and it is not exclusive to ClioSoft Design Management Software. It can run as a stand-alone tool. We are using Cadence with DesignSync to manage data and it works perfectly fine. The software also gives you an opportunity to save the results as a text file which could be saved as one of the design’s views. It’s great for historical data on the design. The tool can also be used for diffing layout views and we are now looking at using it for possibilities in diffing abstracts (as a quick means of checking for possilble LEF changes).

Q: What other uses do you have for VDD?
A: Example if the design engineer added a device or two and changed a port name or added a new port, these new changes would highlight in green and layout will see exacly what changed from previous version without question. If something was removed it would be highlighted in red in the old location.
The VDD tool can also be used on layout views. One would have to decide if that would be worth the time depending on number of changes. It is great if one did a small eco and wants to verify that’s all that changed but I’d not use it for a final sign-off without going through much scrutization first. I do think it could have value though on LEF flows. We have a lot of tools in-house for LEF integreity but for the quick sanity check the VDD tool might have value here. Quickly do check on Abstract both current and previous and see where a change might have occurred. Because it is visually shown in red / green colors one can see if a shift occurred and can easily remedy it. Just a thought though I find most of the value on the schematic diff use. By the way, the VDD can also show these changes in a text file and I had thought that could be useful for saving as a view for historical data of a design.

Q: For layout how do you check LEF versus GDSII? Are you using some XOR process?
A: XOR process of GDSII is time consuming. LEFs are generated from abstracts which are of course generated from layout but what could be done is DIFF two abstracts to do a sanity check that pins have not move (or if moved was to expectations). One could do a diff of lef files too but many times when you discover that there are differences the text file doesn’t give you a quick picture on what changed. One then has to do further work such as GDS compares to see what movements happened. VDD tool can run diff on layouts or anything made of layers in moments. IT puts these changes in 2 colors so you can see old vs new instantaneously. For me it’s just faster and provides the layout designer the information they need to fix or confirm.

Q: Is your group growing?
A: It grew dramatically over past year from approx. 23 to 38.

Summary
Qualcomm uses IC tools from multiple vendors and integrates them into a cohesive EDA tool flow to create complex IP blocks used mostly in cell phones. Transistor-level IC design and layout is alive and well for the high-volume markets that Qualcomm serves.

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