Webinar: Post-layout Circuit Sizing Optimization

My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore, thanks to EDA tools that are quicker and more accurate than manual methods. MunEDA is an EDA vendor that has developed a tool suite for IC design migration, circuit sizing and verification of full-custom IP. They call their tool WiCkeD and are hosting a circuit sizing and optimization webinar on October 4th. Here is a link to the replay.

Michael Pronath from MunEDA will be introducing the concepts of circuit sizing and optimization, where a design engineer starts out with some netlist and then needs to optimize device geometries, like: W, L, # of fins, device fingers, R, C, Vt type, etc. The challenge for designers is to meet the specifications across all of the PVT corners, while improving the yield, power, area, or aging degradation. Manual design optimization approaches are just too slow, so automation is required to help meet project deadlines.

The optimization process starts out with the designer entering specifications, defining how each specification will be bound, then choosing which design parameters are to be optimized. Post-layout optimization takes into account the RC interconnect parasitics, plus the layout-dependent effects (LDE). Four different optimization strategies are introduced for dealing with post-layout parasitics and LDE. The preferred strategy is shown below:

This workflow starts out with a schematic to be optimized, then an initial layout is made, followed by post-layout verification. The optimization loop measures the performance against specifications, then does sizing on the parameters, results update the pre-layout schematic through back annotation, finally the layout is updated. An incremental, sensitivity-based optimizer is used to minimize the number of loops.

Moving from theory to practice, the webinar also includes an actual live demonstration of the entire IC optimization process on an op-amp circuit, with Cadence ADE, Virtuoso schematics, the WiCkeD tool, choosing which W/L devices need tuning, viewing simulation results, using sensitivity analysis. The optimizer in the demo updates the schematic values quickly.

Register now for the replay

About MunEDA
MunEDA develops and licenses EDA tools and solutions that analyze, model, optimize and verify the performance, robustness and yield of analog, mixed-signal and digital circuits. Leading semiconductor companies rely on MunEDA’s WiCkeD’ tool suite – the industry’s most comprehensive range of advanced circuit analysis solutions – to reduce circuit design time and achieve maximum yield in their communications, computer, memory, automotive and consumer electronics designs. Founded in 2001, MunEDA is headquartered in Munich, Germany, with offices in Cupertino, California, USA (MunEDA Inc.), and leading EDA distributors in the U.S., Japan, Korea, Taiwan, Singapore, Malaysia, Scandinavia, and other countries worldwide. For more information, please visit MunEDA at www.muneda.com/contacts.php.

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