Analog Mixed-Signal Layout in a FinFET World

Analog Mixed-Signal Layout in a FinFET World
by Tom Dillinger on 03-20-2016 at 12:00 pm

The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More


Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom … Read More


Cadence ♥ TSMC

Cadence ♥ TSMC
by Daniel Nenni on 04-19-2013 at 6:00 pm

TSMC has been investing in the fabless semiconductor ecosystem for 25+ years and that is why they are the #1 foundry and lead this industry (my opinion). I’m a big fan of joint webinars. Not only is it collaboration open to the masses, it is a close collaboration between the two sponsoring companies. Having worked on the TSMC… Read More


Variation-aware IC Design

Variation-aware IC Design
by Daniel Payne on 04-15-2013 at 4:18 pm

We’ve blogged before about Layout Dependent Effects (LDE) on SemiWiki and how it further complicates the IC design and layout process, especially at 28nm and lower nodes because the IC layout starts to change the MOS device performance. There’s an interesting webinarfrom Cadence on Variation-aware IC Design, … Read More


Virtuoso is 20nm-ready

Virtuoso is 20nm-ready
by Paul McLellan on 01-30-2013 at 1:47 pm

I already talked about how Cadence is splitting Virtuoso into two. Anyway, it is now officially announced. The 6.1 version will continue to be developed as a sort of Virtuoso classic for people doing designs off the bleeding edge that don’t require the new features. And a new Virtuoso 12.1 intended for people doing 20nm and… Read More


TSMC Theater Presentation: Ciranova!

TSMC Theater Presentation: Ciranova!
by Daniel Nenni on 06-14-2012 at 9:00 pm

Ciranova presented a hierarchical custom layout flow used on several large advanced-node designs to reduce total layout time by about 50%. Ciranova itself does automated floorplanning and placement software with only limited routing; but since the first two constitute the majority of custom layout time, and strongly influence… Read More


A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design

A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design
by Eric Filseth on 04-29-2012 at 9:00 pm

At 28nm and below, a number of electrical variation effects become significant which depend not only on individual devices, but the physical interaction between neighboring devices, wells, etc during the manufacturing process. Some of these effects have become collectively referred to as “Layout Dependent Effects” (LDE);… Read More


Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)

Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)
by Daniel Payne on 04-18-2012 at 12:38 pm

Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you’re in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a … Read More