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Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom can we give the trophy if we have one to offer? Okay, then ask a simple question, what’s it without which the design couldn’t have proceeded in the first place in real physical terms and you get the instant answer – it’s PDK. The Process Design Kits may be lesser known in the world of ESL and RTL, but ask a back-end designer and she will tell you can’t do without PDK no matter how powerful EDA tools you have, and it’s utmost important for your PDK to be of highest quality. But then the EDA tools need to drive into the design what PDK has in the most effective manner.

It was a very pleasant moment when I came across a DACpresentation offered by Maq Mannan of GLOBALFOUNDRIES. Although it was a recorded presentation, it was pleasure listening to Maq; it revived my old memories of Cadence. Maq is a veteran in PDK domain; he founded DSM Technologies (which dealt in PDK development automation systems) in late 1990 – early 2000 which got acquired by Cadenceand that formed the PDK group at Cadence headed by Maq. Now Maq is at GLOBALFOUNDRIES, leading and delivering the best PDKs which are of highest quality, flexible and easy-to-use, enabling GF’s leading edge process technologies into SoC designs.

Starting from say 130nm to 20nm and below, added with FinFETs, the number of design rules have increased tremendously (approximately doubled with each node change), and along with it increased number of operations with each rule in the same or higher proportion; multi-patterning added further major complexities. Designers cannot keep track of rules while working. Keeping these in mind, the PDKs from GF have in-built, easy-to-use methods for designers to carry out their work without any loss of productivity. Recently GF and Samsungpartnered for PDKs at 14nm (14LPP and 14LPE) which can go to both the fabs with same design rules, models, DRM etc. thus improving productivity. The 14LPE V1.0 PDK is already released. As the complexities have increased with rapidly advancing technologies, it’s essential for fabs and EDA vendors to collaborate and leverage their capabilities to keep the tools in sync with technology to drive the designs in best possible manner. GF has built strong collaboration with multiple EDA and IP partners. Let’s look at what’s cooking up between GF and Cadence.

GF has major collaboration with Cadence with most of their customers using Virtuoso and Cadence libraries which is very significant and critical to their success. The area is spread across from digital routers to device models, simulation, extraction and verification to DFM kits, and the entire infrastructure relating to those is covered into PDK.

Cadence introduced IPVS which provides in-memory verification (with real-time DRC on edits) of layout within the Virtuoso layout design environment eliminating time consuming StreamIn/Out which was earlier needed by Standalone PVS. This capability is very significant in boosting designers’ productivity. GF supports PVS decks for virtually all technology nodes. This is a capability close to my heart as I always aspired for it in Virtuoso while I managed the physical design part of Virtuoso at Cadence.

Read one my older article on this – 28nm Layout Needs Signoff Quality at Design Time.

At advanced nodes (28nm and below), layout dependent effects (LDE) becomes significant causing significant deviation in device characteristics from their normal behaviour. Cadence tools along with wide range of support in GF’s PDKs to take these effects into consideration provides a versatile layout aware design flow which enables LDE estimation at schematic, detects LDE problems in layout, checks against constraints provided by circuit designers and verifies using LVS the final extracted layout for both placement as well as interconnect effects.

GF also provides decomposition options which are very critical for customers at advanced nodes, a key requirement for multi-patterning.

The designs can be done in colored layers (M1_E1, M1_E2) which is appropriate for standard cells, colorless layer (M1) appropriate for p-cell design and P&R which can be decomposed later by specific tool in PDK or mixed (hybrid) way. GF offers all three methodologies at 20nm; designs can be done in any of these combinations. For 14nm, they are working with Samsung to align on a single approach.

GF provides complete modeling environment with versatile Spice model library containing MOSFETs (RVT, HVT, LVT, SRAM, EG, ZG) including any special memories and devices and Non_FETS (Resistors, Capacitors, Diodes, Fuse and others). Models for variation (MC, Mismatch, and Analog), aging (Reliability) and stress (DSL, STI, WPE etc.) are accounted for.

It’s a great presentation to go through and know about PDKs and CadenceGF collaboration in more detail. It’s freely available here. Click the link against “Collaboration Key to Enablement at Advanced Nodes”.

More Articles by Pawan Fangaria…..

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