MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages

MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages
by Fred Chen on 05-10-2020 at 6:00 am

MOSFET Gate Length Scaling Limit at Reduced Threshold Voltages

As transistor dimensions shrink to follow Moore’s Law, the functionality of the gate used to switch on or off the current is actually being degraded by the short channel effect (SCE) [1-5]. Moreover, the simultaneous reduction of voltage aggravates the degradation, as will be discussed below.

A Practical Lower Limit ofRead More


Tracing Technology’s Evolution with Patents

Tracing Technology’s Evolution with Patents
by Arabinda Das on 04-23-2020 at 10:00 am

Figure 1

We live in an age of abundant information. There is a tremendous exchange of ideas crisscrossing the world enabling new innovative type of products to pop up daily. Therefore, in this era there is a greater need to understand competitive intelligence. Corporate companies today are interested in what other competitors are brewing… Read More


Six Reasons to Rethink Power Semiconductor Packaging

Six Reasons to Rethink Power Semiconductor Packaging
by Alex Lidow on 06-12-2016 at 8:00 pm

In my 40 years’ experience in power semiconductors I have visited thousands of customers, big and small, on every continent except Antarctica. When the issue invariably turns to the packaging of the power semiconductor – transistor, diode, or integrated circuit – the requests for improvement fall into six categories:
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Is GaN Disruptive? Revisiting the Criteria

Is GaN Disruptive? Revisiting the Criteria
by Alex Lidow on 06-07-2016 at 12:00 pm

In March 2010 Efficient Power Conversion (EPC) proudly launched our GaN technology at the CIPS conference in Nuremberg, Germany. Parts and development kits were readily available off-the shelf and therefore designers could immediately get started with a new state-of-the-art semiconductor technology.
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The Importance of Transistor-Level Verification

The Importance of Transistor-Level Verification
by Students@olemiss.edu on 04-10-2016 at 7:00 am

According to the IEEE Std 1012-2012, verification is the acknowledgement that a product is in satisfactory condition by meeting a set of rigorous criteria. [3] Transistor-level verification involves the use of custom libraries and design models to achieve ultimate performance, low power, or layout density. [2] Prediction… Read More


Four Things a New Semiconductor Technology Must Have to be Disruptive

Four Things a New Semiconductor Technology Must Have to be Disruptive
by Alex Lidow on 08-21-2015 at 12:00 pm

This post discusses attributes of gallium nitride (#GaN) that make it a disruptive technology and identifies the four factors required for GaN technology to displace silicon as the technology of choice.

Displacing the Silicon with GaN

38 years ago, when I first entered the semiconductor business as a freshly minted Stanford
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Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom … Read More