TSMC has been investing in the fabless semiconductor ecosystem for 25+ years and that is why they are the #1 foundry and lead this industry (my opinion). I’m a big fan of joint webinars. Not only is it collaboration open to the masses, it is a close collaboration between the two sponsoring companies. Having worked on the TSMC AMS reference flows for the past four years I can tell you that these webinars are definitely worth your time.
Enhance your expertise with two new webinars from TSMC and Cadence!
Addressing Layout-Dependent Effects: At 9am and 6:30pm PDT on April 25, Manoj Chacko and Bala Kasthuri of Cadence and Jason Chen from TSMC will present, “Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects Using the Cadence® Virtuoso® Platform, Part II, a sequel to Variation-Aware Design, Part I. You’ll learn about:
- The solutions jointly developed by Cadence and TSMC, to provide a complete layout-dependent effect (LDE) flow for circuit and layout designers working at 28nm and below
- When, why, and how you should incorporate TSMC’s LDE-API with Cadence Virtuoso tools into an analog, custom, or mixed-signal design flow to achieve the most efficient design cycle time
Register Now: https://www.secure-register.net/cadence/TSMC_Q2_2013
Managing Design Complexity at 20nm: At 9am and 6:30pm PDT on May 23, Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will present, “20nm Design Methodology: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Encounter®, Virtuoso, and Signoff tools.” You’ll learn about:
- The TSMC-Cadence solutions in the TSMC 20nm Reference Flow, tools certification, and Cadence tools and methodology to enable 20nm design with double patterning technology (DPT)-aware capabilities, to reduce design complexities and deliver required accuracy
- How in-design DPT and design rule checking (DRC) can improve your productivity
- How both colored and colorless methodologies are supported, and data is efficiently managed in front-to-back design flows
- How local interconnect layers, SAMEMASK rules, and automated odd-cycle loop prevention are supported
- How mask-shift modeling with multi-value SPEF is supported for extraction, power, and timing signoff
Register today: https://www.secure-register.net/cadence/TSMC_Q2_2013
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