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iPDK is the way to go for AMS designs

iPDK is the way to go for AMS designs
by Daniel Payne on 01-19-2011 at 3:47 pm

294 towerjazz logo1 jpg

I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.

In the old days each foundry would have to staff up… Read More

Variation-aware Design Survey

Variation-aware Design Survey
by Paul McLellan on 01-05-2011 at 5:56 pm

Solidohas run an interesting survey on variation-aware design. The data is generic and not specific to Solido’s products although you won’t be surprised to know that they have tools in this area.

What is variation-aware design? Semiconductor manufacturing is a statistical process and there are two ways to handle this in the design… Read More

Webinar on Accelerating Analog Layout Productivity

Webinar on Accelerating Analog Layout Productivity
by Daniel Payne on 12-08-2010 at 11:58 pm

MONROVIA, California – December 7, 2010 – With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity for analog and mixed-signal design are mission-critical. Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal… Read More

Tanner EDA Then and Now

Tanner EDA Then and Now
by Daniel Payne on 11-26-2010 at 9:44 pm

tanner then now

Looking back at an early issue of a Tanner Research newsletter, “Tanner Tools News”, from the mid-1990s, the theme at that time was growth, just as it is again now for Tanner EDA. At that time we were averaging 66% revenue growth per year, enjoying rapid growth as a small start-up. Fast-forward to current day, where we… Read More

Moore’s Law and 28nm Yield

Moore’s Law and 28nm Yield
by Daniel Nenni on 01-24-2010 at 10:44 pm

This blog is a follow-up to my second most viewed page Moore’s Law and 40nm Yield, with a strong recommendation of how to design for yield at the advanced nodes (32/28/22nm) with Verify High-Sigma design technology.

Case in point: Circuit blocks such as complex standard cells or memory bit cells are repeated thousands or even millions… Read More