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Moore, or More Than Moore?

Moore, or More Than Moore?
by Paul McLellan on 04-19-2013 at 12:05 pm

 Yesterday was the 2013 GSA Silicon Summit, which was largely focused on contrasting what advances in delivering systems will depend on marching down the ladder of process nodes, and which will depend on innovations in packaging technology. So essentially contrasting Moore’s Law with what has come to be known as More Than Moore: 2.5D interposer-based designs using TSV and other innovations.

The first panel was focused on communication. The second on Internet of Things (IoT). Finally, the third was on integration challenges.

The industry is preparing for a 1000X increase in traffic (for example, data volumes doubled between 2010 and 2011). But there are major challenges. Moore’s Law is slowing down and cost reduction (per transistor) with each process node is dubious or not happening. On air interfaces we are now close to the Shannon limit of information/Hz. Integrating RF onto CMOS (especially in FinFET) is an opportunity/challenge. Advances in packaging technology, especially those that allow a mix of die in the same package, offer alternative ways of assembling systems if the cost can be got under control.

There seemed to be general acceptance that 20nm is not going to be significantly cheaper than 28nm which has a few implications:

  • 28nm will be a very long lived node
  • there may be opportunities for innovation at 28nm such as fully-depleted options to get many of the advantages (especially low power) of moving to 20nm without the additional cost (due to double patterning in particular)
  • cost-sensitive designs will not go to 20nm unless the volumes are enormous but premium products that can take advantage of the extra gates and lower power will eat the cost
  • old nodes such as 0.13um and 0.18um will continue to be important, and in fact these are both currently growth nodes
  • the cost of moving to 20nm is not just the wafer cost but the development cost, so it needs $Bs of revenue to justify
  • IP availability may be as important when moving to a new node, as process availability. SoC design groups cannot afford to design all their own Serdes, Phys etc

There seemed to be a general feeling that true 3D won’t happen any time soon, but 2.5D interposer-based designs will play a big role in the next few years. The two big challenges are that silicon interposers are expensive and organic interposer (what some people called 2.1D) may be better. The other problem big problem is thermal, getting the heat out from the design.

However, another driver for the More Than Moore packaging approach may be that “split chips” become important because analog turns out to be too difficult in FinFET, which has quantized transistor sizes. So analog (and RF) may need to be left outside the main SoC as we move down the process nodes.

Another packaging driver in the mobile market appears to be that RF front ends won’t have integrated filters (on-chip) so they will need to be integrated into the package to get close to the IC.

So Moore and More Than Moore are going to be required in the coming years.

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