Tag: interposer

Webinar: Thermal Integrity Challenges and Solutions of Silicon Interposer Design

Webinar: Thermal Integrity Challenges and Solutions of Silicon Interposer Design
by Admin on 03-07-2023 at 2:27 am

In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation will cover thermal hotspots, mechanical stresses induced by thermal issues, and methods for capturing these problems with simulation and virtual prototyping,

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Interconnect Choices for 2.5D and 3D IC Designs

Interconnect Choices for 2.5D and 3D IC Designs
by Daniel Payne on 02-14-2023 at 10:00 am
Categories: EDA, Siemens EDA

STCO min

A quick Google search for “2.5D 3D IC” returns 669,000 results, so it’s a popular topic for the semiconductor industry, and there are plenty of decisions to make, like whether to use an organic substrate or silicon interposer for interconnect of heterogenous semiconductor die. Design teams using 2.5D and … Read More

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Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks

Driving PPA Optimization Across the Cubic Space of 3D IC Silicon Stacks
by Tom Simon on 07-06-2021 at 9:00 am
Categories: EDA, Synopsys

Improved PPA Using 3D IC

The move to true 3D IC, monolithic 3D SOC and 3D heterogeneous integration may require one of the most major design tool architecture overhauls since IC design tools were first developed. While we have been taking steps toward 3DIC with 2.5D designs with interposers, HBM, etc., the fundamental tools and flows remain intact in many… Read More

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Cadence Continues Photonics Industry Engagement

Cadence Continues Photonics Industry Engagement
by Daniel Nenni on 12-17-2019 at 10:00 am
Categories: Cadence, EDA, Events, Silicon Photonics

On November 13, Cadence held its annual Photonics Summit. Cadence has been hosting this event for several years with the intention of advancing the photonics industry. With this event, Cadence has been a catalyst in furthering photonic product development. It’s quite remarkable that Cadence hosts such an event in a field where… Read More

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Mentor unpacks LVS and LVL issues around advanced packaging

Mentor unpacks LVS and LVL issues around advanced packaging
by Tom Simon on 11-26-2019 at 6:00 am
Categories: EDA, Siemens EDA

Innovations in packaging have played an important role in improving system performance and area utilization. Advances like 2.5D interposers and fan-out wafer-level packaging (FOWLP) have allowed mixed dies to be used in a single package and have dramatically reduced the number of connections that need to go all the way to the… Read More

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Power Integrity from 3DIC to Board

Power Integrity from 3DIC to Board
by Bernard Murphy on 09-14-2017 at 7:00 am
Categories: Ansys, Inc., EDA

The semiconductor industry has built decades of success on hyper-integration to increase functionality and performance while also reducing system cost. But the standard way to do this, to jam more and more functionality onto a single die, breaks down when some of the functions you want to integrate are built in different processes.… Read More

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HBM offers SOC’s dense and fast memory options

HBM offers SOC’s dense and fast memory options
by Tom Simon on 08-22-2017 at 7:00 am
Categories: IP, Synopsys

Dual in-line memory modules (DIMM’s ) with double data rate synchronous dynamic random access memory (DDR SDRAM) have been around since before we were worried about Y2K. Over the intervening years this format for provisioning memory has evolved from supporting DDR around 1995, to DDR1 in 2000, DDR2 in 2003, DDR4 in 2007 and DDR4… Read More

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It’s Time to Stop Thinking in Two Dimensions

It’s Time to Stop Thinking in Two Dimensions
by Tom Simon on 05-03-2017 at 12:00 pm
Categories: eSilicon, Semiconductor Services

The first transistor was made of two electrodes, held in place by plastic, making contact with a piece of doped germanium. Ever since then, devices and their packaging have been performing a complicated and oftentimes intricate dance. Single transistor devices became integrated circuits, and along the way separate IC’s were… Read More

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16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP

16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP
by Tom Simon on 09-29-2016 at 12:00 pm
Categories: FinFET, IP, Open-Silicon

Once a year, during the TSMC’s Open Innovation Platform (OIP) Forum you can expect to see cutting edge technical achievements by TSMC and their partners. This year was no exception, with Open-Silicon presenting its accomplishments in implementing an HBM reference design in 16nm. It’s well understood that HBM offers huge benefits… Read More