Unlocking the Full Potential of Soft IP

EDA vendors, IP suppliers and Foundries provide an eco-system for SoC designers to use in getting their new electronic products to market quicker and at a lower cost. An example of this eco-system are three companies (TSMC, Atrenta, Sonics) that teamed up to produce a webinar earlier in March called: Unlocking the Full Potential of Soft IP.

Introduction
Daniel Nenni, founder of SemiWiki was the moderator and he talked about the importance of Soft IP. A typical 20nm SoC can use 190 or more IP blocks, with a development cost of $164M. Do you have the time to verify each of these IP blocks, can you optimize power, performance and cost? Can you deliver your SoC on time?

A report from International Business Strategies showed design implementation costs and number of IP blocks per design from several process nodes: 90nm, 65nm, 45/40nm, 32/28nm, 22/20nm.

TSMC Soft-IP Alliance Program
Deputy Director Dan Kochpatcharin was up next in the webinar and the first thing he brought up was IP quality and availability, a set of questions they ask for each new IP partner. TSMC has some 40+ IP providers that have been qualified.

With all of these IP partners TSMC has some 5,000 IP blocks available publicly, with 10,000 IP blocks available internally. Most of the IP has been historically hard IP, so starting in 2010 the soft IP was added because tighter collaboration was required to meet Power, Performance and Area (PPA) metrics. There are 16 partners in the Soft IP Alliance Program to date.

Quality is ensured with soft IP by doing RTL Code Assessment, an optional physical implementation, and IP usage tracking during volume production. Atrenta software tools are used to do the quality checking of soft IP. At the design portal of TSMC a designer can search both soft and hard IP to view the quality assessment.

Companies like ARM, MIPS and Imagination work together with TSMC to co-optimize the soft IP to reach different PPA goals. This cooperation between foundry and IP supplier reduces the risk, and shortens design time.

Soft IP Quality
Mike Gianfagna from Atrenta spoke about how to assess soft IP in an automated fashion. What they’ve put together is an IP kit that combines an assessment methodology, automation, IP design intent and IP reports:

The learning curve for using the IP Kit is lowered by using the Quickstart guide and training module. Feedback on the IP quality is reported as a dashboard and datasheet, viewable in a web browser. Colors are used to convey feedback, like Yellow for warning, Green for pass and Red for failure. Design objectives and quality goals are readily available.

The dashboard can show designers Power goals over design time, or the number of errors and warnings, useful metrics for the program manager. In 2011 Atrenta technology was first used by TSMC to measure soft IP quality. Checks inside of the IP handoff kit include metrics for:

• Power
• Clocks & Timing
• Lint
• Testability
• Physical Implementation

Using this soft IP quality assessments the Atrenta software has identified issues in IP partner blocks prior to silicon, saving SoC designers debug and re-spin efforts.

Soft IP Provider
Our final speaker was John Bainbridge, Staff Technologist with Sonics and his presentation focused on what it’s like for a a soft IP company to meet the quality metrics required. SONICS has interconnect IP that allows other IP blocks to communicate together on an SoC. Their customer list is impressive looking and covers consumer electronic, semiconductor and other IP providers:

On-chip networks allow diverse IP to be connected together. Sonics can help SoC designers with scaling their methodology, throughput, power consumption and memory scheduling within the interconnect.

Sonics interconnect could use crossbar technology, or serial links, all depending on the physical layout and timing constraints you need to meet:

A GUI is used to configure the interconnect with various interface protocols:

Output from Sonics includes SystemC models, Verilog RTL, design constraints, Synthesis scripts and validation. The Verilog RTL is then run through the Atrenta tools to test metrics like:

• Power

  • Average power dissipation
  • Power comans check
• Clocks and Timing

  • Clocks and reset constraints
  • Consisten, Correct and complete clock definitions
  • Clock domain crossing sychronizers
  • Consistent timign constraints acros block boundaries
  • False path and multi-cycle paths checkes
• Lint – is the design ready for simulation and synthesis
• Test Coverage
• Physical – routing congestion checks

John showed actual Atrenta DashBoard results, where they get feedback on the IP quality and where they create waivers to reach their low power goals. Sonics was a beta partner to validate the TSMC Soft IP 2.0 Kit program. IP quality can be designed and measured now with this program.

Q&A
Q: Does the business model change after an IP vendor joins the Soft IP program?
A: TSMC – We don’t get involved in-between the SoC designer and the IP provider of choice.

Q: What benefits of this alliance program have you seen?
A: Sonics – We showed one dashboard example using Atrenta tools. With this approach we now have a standardized ruleset to pass and show our IP quality.

Q: What customer benefits are their to customers?
A: Atrenta – really it’s risk reduction and schedule improvements. Finding the problems earlier in the process does shorten design times.

Q: How do you join the Soft IP Alliance program?
A: TSMC – You contact us, Richard Lee, and he will walk you through that process.

Q: What are the focus IP blocks?
A: TSMC – Controllers, GPU, CPU, Interconnect IP.

Q: What issues can you find with your IP after running Spyglass?
A: Sonics – Typically we find minor lint issues in our IP. It took a few days for our AE to get the Atrenta flow setup and start running tests.

Q: How long does it take to learn using the IP kit?
A: Atrenta – We use webex training sessions in a few hours to show how to use the IP kit. After a few hours of training, the users are up and running on their own.

Q: For the slide showing the number of IP blocks as a function of foundry node, was that an average number?
A: Atrenta – Those numbers were averaged across a few dozen company examples.

Q: How do Spyglass results track versus physical implementation tools?
A: Atrenta – The results of Spyglass for predicting fault coverage have been within 1% of DFT tools. Power estimation is about 10% to 15% of detailed tools. Synthesis and simulation comparisons are quite accurate.

Full Webinar
To view the full webinar takes 54 minutes and is online here.

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