Webinar 800x100 (1)
WP_Term Object
(
    [term_id] => 14433
    [name] => X-Subscriber
    [slug] => x-subscriber
    [term_group] => 0
    [term_taxonomy_id] => 14433
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 0
    [filter] => raw
    [cat_ID] => 14433
    [category_count] => 0
    [category_description] => 
    [cat_name] => X-Subscriber
    [category_nicename] => x-subscriber
    [category_parent] => 0
    [is_post] => 
)

Image Sensor Design for IR at Senseeker

Image Sensor Design for IR at Senseeker
by Daniel Payne on 03-05-2013 at 10:30 am

Image sensors are all around us with the cell phone being a popular example, and 35mm DSLR camera being another one. Last week I spoke with Kenton Veeder, an engineer at Senseeker that started his own image sensor IP and consulting services company. Instead of focusing on the consumer market, Kenton’s company does sensor … Read More


TSMC ♥ Atrenta (Soft IP Webinar)

TSMC ♥ Atrenta (Soft IP Webinar)
by Daniel Nenni on 03-02-2013 at 4:00 pm

Back in 2011, TSMC announced it was extending its IP Alliance Program to include soft, or synthesizable IP. Around that time it was also announced that Atrenta’s SpyGlass platform would be used as the sole analysis tool to verify the completeness and quality of soft IP before being admitted to the program. Since then, the … Read More


OTP based Analog Trimming and Calibration

OTP based Analog Trimming and Calibration
by Eric Esteve on 03-01-2013 at 10:16 am

Embedded NVM technology based functions can be implemented in large SoC designed in advanced technology nodes down to 28nm, as there is no requirement for extra mask levels, like when integrating Nand Flash, negatively impacting the final cost. And it is also possible to integrate One Time Programmable (OTP) to store trim and … Read More


Using Soft IP and Not Getting Burned

Using Soft IP and Not Getting Burned
by Daniel Payne on 02-07-2013 at 10:11 am

The most exciting EDA + Semi IP company that I ever worked at was Silicon Compilers in the 1980’s because it allowed you to start with a concept then implement to physical layout using a library of parameterized IP, the big problem was verifying that all of the IP combinations were in fact correct. Speed forward to today and our… Read More


A Brief History of Tanner EDA

A Brief History of Tanner EDA
by Daniel Nenni on 01-28-2013 at 11:00 pm

While founder John Tanner, PhD, got his initial exposure to the TTL Cookbook and CMOS Cookbook as an undergraduate, it was his experience as a Caltech graduate student that forged his early path in EDA. In 1979, while enrolled in a VLSI design course at Caltech, John and his classmates received a pre-print of Carver Mead’s seminal… Read More


A Brief History of Sidense

A Brief History of Sidense
by Daniel Nenni on 01-24-2013 at 9:00 pm


Sidense Corp. is a leading developer of embedded non-volatile memory (NVM) intellectual property (IP) for the semiconductor IC market. The company is headquartered in Ottawa, Canada, and has a global presence with sales offices worldwide.

The company was founded in 2004 by CTO Wlodek Kurjanowicz, a MoSys fellow and co-founder… Read More


How We Got Here…

How We Got Here…
by Paul McLellan on 01-22-2013 at 12:54 pm

Over at the GSA Forum website I have an article on the history of the semiconductor industry. It is actually based on a couple of brief history of semiconductor blogs (here and here) I published here on SemiWiki last year but edited down a lot and tightened up.

Since the start of the year seems to be the time for predictions, here are the… Read More


FD-SOI is Worth More Than Two Cores

FD-SOI is Worth More Than Two Cores
by Paul McLellan on 01-20-2013 at 10:00 pm

This is the second blog entry about an ST Ericsson white-paper on multiprocessors in mobile. The first part was here.

The first part of the white-paper basically shows that for mobile the optimal number of cores is two. It is much better to use process technology (and good EDA) to run the processor at higher frequency rather than add… Read More


OTP @ 2013 Common Platform Technology Forum

OTP @ 2013 Common Platform Technology Forum
by Daniel Nenni on 01-06-2013 at 9:00 pm

Sidense will be exhibiting at the Common Platform Technology Forum in Santa Clara, California on February 5, during which time they will be discussing their one-transistor, one-time programmable (1T-OTP) memory IP products. Based on their patented 1T-Fuse™ bit cell, Sidense antifuse-based 1T-OTP macros offer a secure, reliable,… Read More


A Brief History of the MIPS Architecture

A Brief History of the MIPS Architecture
by IMGJen on 12-07-2012 at 1:00 pm

MIPS is one of the most prolific, longest-living industry-standard processor architectures, existing in numerous incarnations over nearly three decades.

MIPS has powered products including game systems from Nintendo and Sony; DVRs from Dish Network, EchoStar and TiVo; set-top boxes from Cisco and Motorola; DTVs from Samsung… Read More