WP_Term Object
(
    [term_id] => 16
    [name] => Moortec
    [slug] => moortec
    [term_group] => 0
    [term_taxonomy_id] => 16
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 33
    [filter] => raw
    [cat_ID] => 16
    [category_count] => 33
    [category_description] => 
    [cat_name] => Moortec
    [category_nicename] => moortec
    [category_parent] => 14433
    [is_post] => 
)
            
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WP_Term Object
(
    [term_id] => 16
    [name] => Moortec
    [slug] => moortec
    [term_group] => 0
    [term_taxonomy_id] => 16
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 33
    [filter] => raw
    [cat_ID] => 16
    [category_count] => 33
    [category_description] => 
    [cat_name] => Moortec
    [category_nicename] => moortec
    [category_parent] => 14433
    [is_post] => 
)

Accuracy of In-Chip Monitoring for Thermal Guard-banding

Accuracy of In-Chip Monitoring for Thermal Guard-banding
by Daniel Payne on 01-28-2019 at 12:00 pm

I remember working at Intel and viewing my first SPICE netlist for a DRAM chip, because there was this temperature statement with a number after it, so being a new college graduate I asked lots of questions, like, “What is that temperature value?”

My co-worker answered, “Oh, that’s the estimated junction… Read More


Making AI Silicon Smart with PVT Monitoring

Making AI Silicon Smart with PVT Monitoring
by Tom Simon on 11-26-2018 at 7:00 am

PVT – depending on what field you are in those three letters may mean totally different things. In my undergraduate field of study, chemistry, PVT meant Pressure, Volume & Temperature. Many of you probably remember PV=nRT, the dreaded ideal gas law. However, anybody working in semiconductors knows that PVT stands … Read More


A Smart Way for Chips to Deal with PVT Issues

A Smart Way for Chips to Deal with PVT Issues
by Tom Simon on 10-30-2018 at 7:00 am

We have all become so used to ‘smart’ things that perhaps in a way we have forgotten what it was like before many of the things we use day to day had sensors and microprocessors to help them respond to their environment. Cars are an excellent example. It used to be commonplace to run down your battery by leaving your lights on. Now cars … Read More


Make Versus Buy for Semiconductor IP used in PVT Monitoring

Make Versus Buy for Semiconductor IP used in PVT Monitoring
by Daniel Payne on 10-01-2018 at 12:00 pm

As an IC designer I absolutely loved embarking on a new design project, starting with a fresh, blank slate, not having to use any legacy blocks. In the early 1980’s we really hadn’t given much thought to re-using semiconductor IP because each new project typically came with a new process node, so there was no IP even ready… Read More


Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that

Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
by Daniel Payne on 08-24-2018 at 12:00 pm

There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More


Optimization and Reliability for FinFET designs at #55DAC

Optimization and Reliability for FinFET designs at #55DAC
by Daniel Payne on 07-25-2018 at 7:00 am

TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what’s new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time… Read More


Monitoring Process, Voltage and Temperature in SoCs, webinar recap

Monitoring Process, Voltage and Temperature in SoCs, webinar recap
by Daniel Payne on 04-26-2018 at 4:00 pm

Have you ever wondered how process variation, thermal self-heating and Vdd levels affect the timing and yield of your SoC design? If you’re clock specification calls for 3GHz, while your silicon is only yielding at 2.4GHz, then you have a big problem on your hands. Such are the concerns of many modern day chip designers. To… Read More


Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs

Webinar Alert – Embedded Monitoring of Process and Voltage in SoCs
by Daniel Payne on 03-13-2018 at 12:00 pm

In the old days to learn about new semiconductor IP you would have to schedule a sales call, listen to the pitch, then decide if the IP was promising or not. Today we have webinars which offer a lot less drama than a sales call, plus you get to ask your questions by typing away at the comfort of your desk, hopefully wearing headphones as … Read More


Why It’s A Good Idea to Embed PVT Monitoring IP in SoCs

Why It’s A Good Idea to Embed PVT Monitoring IP in SoCs
by Daniel Payne on 02-16-2018 at 7:00 am

At Intel back in the late 1970’s we wanted to know what process corner each DRAM chip and wafer was trending at so we included a handful of test transistors in the scribe lines between the active die. Having test transistors meant that we could do a quick electrical test at wafer probe time to measure the P and N channel transistor… Read More


Moore’s Law Drives Foundries and IP Providers

Moore’s Law Drives Foundries and IP Providers
by Daniel Payne on 01-19-2018 at 7:00 am

2017 was a banner year for semiconductor sales as they topped $400B for the first time, an increase of some 20%, there is happiness in Silicon Valley, Taiwan, South Korea, and well, everywhere. With the foundries pushing to ever-smaller process dimensions and even going back to mature nodes and offering more variations that are… Read More