As an IC designer I absolutely loved embarking on a new design project, starting with a fresh, blank slate, not having to use any legacy blocks. In the early 1980’s we really hadn’t given much thought to re-using semiconductor IP because each new project typically came with a new process node, so there was no IP even ready for re-use, at least not at the IDM that I worked at. In 2018 by stark contrast we now have a thriving IP economy providing IC designers with everything starting from simple logic functions at the low-end, all of the way up to processors at the high-end, plus every kind of AMS function that you can imagine. My former Intel co-worker Chris Rowen once famously stated, “The processor is the new NAND gate.”
So let’s say that your next SoC has a power budget, timing specifications and thermal reliability metrics, so you naturally want to have PVT (Process, Voltage, Temperature) monitors placed around your chip in strategic locations so that you can measure and control everything, but should you create your own IP from scratch or just buy something off the shelf? Great question.
Let’s make a quick list of what it might take to develop your own PVT blocks and start using them:
- Analog IC design skills, do we need to hire someone
- Expertise to achieve high accuracy from in-chip monitors, with smallest die size and robust operation
- Awareness of legal positioning (patents, design rights, trademarks)
- Budget for EDA tools for analog IC design
- Design time and effort
- Budget for test chip and mask costs
- Understanding of fabrication and device packaging timescales
- Awareness of silicon validation and debug time
- Contingencies for test chip iteration before production use, allowance for refining the design to meet specifications
- Understanding and expertise to know where to place each monitor and how many monitor instances to place an SoC for a given application
According to the website www.payscale.com the total pay for an analog IC design engineer ranges between $74,378 and $182,461 per year, with a median pay at $105,979.
You also want that Analog IC design engineer to have experience making PVT monitors from 40nm down to FinFET process nodes, with working silicon as proof.
Each PVT instance has to be accurate enough to feed back data to a digital controller that then makes decisions about DVFS (Dynamic Voltage Frequency Scaling), clock throttling, or changing VDD levels to meet specs and enhance reliability. If the accuracy of the sensor is off, then the control decisions will be inefficient or worst case harm the chip operation or fail to meet the specs.
Other IP vendors have created their own PVT monitors and may have patented them, so you need to ensure that your novel IP designs and techniques aren’t infringing an existing patent. There were 141 semiconductor patent suits in 2013 for US District Court Cases.
Source: Jones Day
The lawyers get rich in patent disputes and both parties drain their precious financial savings downwards until a victor is established. In many cases the patent victor is able to batter the losing company down enough to either bankrupt them or cause them to be acquired, not a pretty sight.
EDA tools for an analog IC designer include:
- Schematic Capture
- Circuit Simulation (SPICE)
- Layout Tool
- Schematic-driven Layout
- Parasitic Extraction
- Reliability analysis
- Transistor Sizing
- Design centering with Monte Carlo analysis
- IR Drop analysis
- Electromigration analysis
For the digital controller portions you’ll likely need:
- HDL entry
- Logic synthesis
- Static Timing Analysis
- Place & Route
- DFT tools
The PVT sensors themselves are largely analog while the controller is digital, so more tools for co-simulation will be required:
- AMS simulation and verification
Getting all of the PVT monitor blocks designed and implemented is going to take time, probably on the order of many man-years effort, so add that figure up in your total calculations for making the IP.
Mask costs are highly dependent on the process node that you’re at, so 40nm is about $900K while 28nm masks are about $1.5M, and the costs get steeper. You’re going to need a test chip with the new PVT monitors on to really be certain.
Test chip costs depend on the process node, die size and foundry partner that you choose. Contact your local account manager and get a figure to work with.
Fabrication time depends on the foundry, their capacity at the moment, and whether you are using a multi-project wafer or not. Think weeks to months of time just waiting, when you could certainly be doing something more productive with your engineering staff.
The magic moment is when packaged parts or a raw wafer are delivered and you get to debug your first silicon, engineers and test engineers huddle around and make frantic measurements, debugging their test program, maybe several days to determine if your new IP is working properly across voltage and temperature range. Worst case you’ll find some functional bugs or see that the design doesn’t quite meet the accuracy of your on-chip monitor requirements, so a re-spin is required, sending you back to iterate which will take you more weeks of design, verification and fabrication again.
Even when your PVT IP is working, you now have to be judicious in where to place each sensor and the controller portion in order to optimize SoC-level performance or to fully enhance device lifetime.
If this process outline above sounds laborious, error-prone, engineering heavy, expensive and defeating to your corporate goals of time to market, then just know the alternative is to purchase your PVT in-chip monitoring IP from a trusted vendor like Moortec. I’ve been talking with these folks over the past year and am rather impressed because of these factors:
- 8 years of commercial experience with PVT monitoring subsystems
- 60+ customers to date using their IP
- Consumer Electronics (Digital TV, Mobile, Notebooks, SSD)
- Datacenter (AI, Networking, Enterprise, Cloud Computing, HPC)
- IOT (Wearables, Smart Home, Smart City)
- Automotive (Infotainment, Collision Avoidance, Autonomous Driving)
- Cyrpto-currency Mining (Bitcoin, Litecoin, Etherium)
- IP working in 40nm down to 7nm
Here’s a high-level view of their PVT subsystem:
Every SoC design project has the same decision to make about using PVT in-chip monitoring, make or buy. Hopefully you do some back of the envelope calculations on the make side, then give the folks at Moortec a call to help complete the comparison. Most markets are moving so fast that efficient deployment of your internal design teams, combined with the ever-present time to market pressures, dominate business decisions. So, using trusted IP from a vendor like Moortec sounds like the lowest risk, fastest route to market.
- Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
- Monitoring Process, Voltage and Temperature in SoCs, webinar recap
- Moore’s Law Drives Foundries and IP Providers
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