In this, the second part of a two-part series we delve further into defining worst case, this time focusing specifically on device performance.
In the last blog we talked about the steady increase in power density per unit silicon area and how worst case is definitely getting worse. We discussed how in each new FinFET node the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal activity and supply variation.
Worst Case Performance
Today there is no clear “worst case”. Worst case is very application, design and customer specific. Different applications may have different worst case temperature, voltage and RC corners and the art is in optimizing and not under or over specifying the guard bands.
For FinFET processes we see increased gate capacitance. Interconnect resistances are increasing with each node and track to track spacing is reducing, which means increased interconnect capacitance. Temperature inversion for some but not all types of transistors can mean certain types of transistor usually with higher threshold voltages become unexpectedly faster at higher temperatures/lower supply voltages, whereas transistors on the same chip designed with low threshold voltages may do the opposite and reduce in speed under the same conditions. Worst case then depends on which type of transistor dominates critical paths within the chip.
Process variations are now so large that designing for worst case and including wide guard bands is no longer seen as a valid approach. It simply leaves too much of the performance advantages of moving to a smaller node under-utilised. New approaches are needed which minimize the guard bands and optimise supply voltages on a per chip basis. At a first level, data gained from sensing the supply voltage directly at the logic blocks on chip can be used to optimize the PMIC supply voltages. But more sophisticated schemes such as voltage scaling involve optimization on a per die basis.
Voltage Scaling Schemes
A range of schemes, including SVS (Static Voltage Scaling) and DVFS (Dynamic Voltage and Frequency Scaling) target reducing voltage guard bands on a per die basis whilst ensuring reliable operation. One method implements these by co-locating in-chip sensors next to critical circuit blocks and using Process Detectors to track the performance. Significant saving in production test time to determine the SVS/DVFS operating voltages is possible with this approach.
Prior Planning Prevents Poor Performance!
How close to the limit do SoC development teams get? We see most if not all SoC teams pushing the limits to extract maximum performance whether that is maximising processing power in AI, minimising power consumption for Smart Phones or maximising reliability in automotive. In-chip monitoring is an essential tool, as it gives development teams visibility of real time on chip conditions – essential in the bring up, characterisation and optimization of new silicon. Occasionally we come across teams who wish they had included more in chip monitors, as when you have a problem or want to gain the maximum performance, it is extremely useful to have embedded real time monitors.
In the previous blog we talked about the end of Dennard Scaling with the power per sq. nm steadily increasing with each new geometry node. This combined with increased process variation means ‘worst case is getting worse’! SoC development teams are faced not just with resolving traditional worst case performance issues such as timing but also worst case power. The latter can lead to multiple potential hotspots, temperature gradients and also difficult to predict voltage drops across large SoCs.
Embedding a fabric of accurate in-chip monitors on SoCs provides excellent visibility of on-chip conditions. This is seen as an essential tool for bring up, characterization and optimization on a per die basis especially for SoC development teams who are pushing the limits in their designs, yet want to stay on the right side in worst case conditions.
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