During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same time achieving the greatest data throughput?
I’ve read about AI chips that have billions to even trillions of transistors, and that’s a huge challenge in several areas:
- Localized junction temperatures impact performance and reliability
- IR drop caused by transient switching currents increases timing delays
- Process variations are localized and effect performance
In the 1970s we placed process monitor IP into the scribe lines of each wafer in order to answer some of these questions about process variation, but at the 40nm node and smaller nodes, we really need to have IP embedded within an SoC to understand what the local junction temperature is, how the VDD level is responding to noise, and which process corner the transistors are operating under.
Moortec is a UK-based IP provider that has delivered embedded in-chip sensors and monitoring to address these challenges for SoC design across several disciplines:
- Data Center
With an accurate in-chip voltage monitor your design engineers can implement appropriate voltage scaling approaches:
- Static Voltage Scaling
- Dynamic Voltage Scaling
- Adaptive Voltage Scaling
Register to view this webinar on Thursday, May 7th, 10AM PDT (6pm BST). There are two presenters and Daniel Nenni from SemiWiki is the host:
The company have been providing innovative embedded subsystem PVT IP solutions for over a decade, empowering their customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm & 5nm.