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Webinar: Accelerate time to success using smart methods for DFT chip architecture and validation
May 2 @ 9:00 AM - 10:00 AM
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs.
The Veloce hardware-assisted verification system can efficiently handle large, full-chip GLE designs. Tessent Streaming Scan Network (SSN), a once-in-a-decade technology, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN, as well as other test functions such as TestKompress, BIST pattern validation, functional fault grading, power profiling and estimation, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success.
Target audience:
- DFT Engineers
- DFT Managers
- Product and Test Engineers and Managers
What you will learn:
- Introduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns
- DFT Power Profiling and Fault grading using Veloce Power App
- Applying SSN to solve the Veloce chip design challenges
Speakers:
Product Manager, Verification, Siemens EDA
Robert Serphillips has worked in the pre-silicon verification, post-silicon validation, and production design-for-test (DFT) fields. He has designed and debugged ATE test patterns on multiple stand alone and SoC devices spanning close to 20 years in the semiconductor industry. The products include a mix of consumer, automotive, industrial, military, networking and mixed signal. Robert is currently a product manager with the Siemens EDA hardware-assisted verification business unit.
Sr. Director of Technology Enablement, Tessent, Siemens EDA – Tessent
Ron Press, a 30-year veteran of the test and DFT industry, is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching and on 3D DFT. He started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995.
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