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Intel’s Back to the Future Buy of Micron

Intel’s Back to the Future Buy of Micron
by Ed McKernan on 08-19-2011 at 5:14 am


In an interview that Gordon Moore gave in early 2000, the former co-founder of Intel recounted how they abandoned the DRAM market in the early 1980s in order to exit the increasingly unprofitable business and focus on the promising, yet still young x86 processor market. Intel was also home to EEPROM and NOR Flash, two memory technologies… Read More


Will AMD Crash Intel’s $300M Ultrabook Party?

Will AMD Crash Intel’s $300M Ultrabook Party?
by Ed McKernan on 08-14-2011 at 7:00 am

Let’s face it, the ships are burning in the harbor and there is only one way out of here for AMD. It needs to crash Intel’s exclusive $300M Ultrabook Party in order to grab a slice of the future, more profitable PC market.

Intel Capital Creates $300 Million Ultrabook FundRead More


Smartphones shipments, Sky is the limit…

Smartphones shipments, Sky is the limit…
by Eric Esteve on 08-08-2011 at 8:50 am

…or a global recession, but that’s not the purpose of this blog. As everybody knows, Apple is designing and selling smartphones, only. Does it mean that only smartphones are generating profit in the mobile industry? As we have seen recently in Semiwiki, Apple makes 2/3 of profit of entire mobile industry.

Let’s have a look (below)… Read More


Apple Strength Will Compel ARM to Trim its Sails

Apple Strength Will Compel ARM to Trim its Sails
by Ed McKernan on 08-03-2011 at 7:00 pm

ARM’s move into the broad Tablet and PC space is based on lining up as many partners as possible to attack Intel from multiple angles. It’s a strategy not so different from what Intel employed in the early PC days. However, the strategy is unraveling as Apple and Samsung have reached market share domination without ARM’s merchant… Read More


MCU Performance Customers: The Cavalry is Coming Over The Hill

MCU Performance Customers: The Cavalry is Coming Over The Hill
by Ed McKernan on 07-31-2011 at 7:30 pm

cavalry lg

The under the radar, sleepy microcontroller market is about to undergo a rapid transformation the next several years with new entrants and the rise of 32 bit cores that will redefine the parameters for success. This will revive growth and result in new winners and losers. But lots of questions remain.

My first job out of college in… Read More


Cache Coherency and Verification Seminar

Cache Coherency and Verification Seminar
by Paul McLellan on 07-27-2011 at 5:45 pm

At DAC Jasper presented a seminar with ARM on cache coherency and verification of cache coherency. The seminar is now available online for those of you that missed DAC or missed the seminar itself.

Cache architectures, especially for multi-core architectures, are getting more and more complex. Techniques originally pioneered… Read More


Intel’s Mobile Deja Vu All Over Again Moment

Intel’s Mobile Deja Vu All Over Again Moment
by Ed McKernan on 07-26-2011 at 12:49 pm

We have been here before… and when I say “we” I do include myself. Back in 1997, I joined a secretive company called Transmeta. The company was two years old and working on a new x86 microprocessor to challenge Intel. The original focus of the company was not to build a lower power processor, but one that was faster. As with… Read More


Intel’s Barbed Wire Fence Strategy

Intel’s Barbed Wire Fence Strategy
by Ed McKernan on 07-21-2011 at 11:38 am

Analysts tend to make judgments regarding Intel based on an existing conventional wisdom (CW) and projecting straight line into the future. As a former Intel, Cyrix, and Transmeta processor marketing guy I would like to offer a different perspective as I have been both inside the tent looking out and outside looking in.

The current… Read More


And it’s Intel at 22nm but wait, Samsung slips ahead by 2nm…

And it’s Intel at 22nm but wait, Samsung slips ahead by 2nm…
by Paul McLellan on 07-12-2011 at 12:46 pm

Another announcement of interest, given all the discussion of Intel’s 22nm process around here, is that Samsung (along with ARM, Cadence and Synopsys) announced that they have taped out a 20nm ARM test-chip (using a Synopsys/Cadence flow).

An interesting wrinkle is that at 32nm and 28nm they used a gate-first process but… Read More


On-chip supercomputers, AMBA 4, Coore’s law

On-chip supercomputers, AMBA 4, Coore’s law
by Paul McLellan on 07-11-2011 at 12:45 pm

At DAC I talked with Mike Dimelow of ARM about the latest upcoming revision to the AMBA bus standards, AMBA 4. The standard gets an upgrade about every 5 years. The original ARM in 1992 ran at 10MIPS with a 20MHz clock. The first AMBA bus was a standard way to link the processor to memories (through the ARM system bus ASB) and to peripherals… Read More