Timing for TSMC Wafer Orders
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Dougwithau
New member
Ask you FAE. How many wafers are in your order?
If you don't have an FAE, you don't want to be on an advanced node. The process flow duration may be closely held and not something they want customers to compare.
If you don't have an FAE, you don't want to be on an advanced node. The process flow duration may be closely held and not something they want customers to compare.
fansink
Active member
Thanks, I'm asking out of interest, not as a potential customer.
I've heard that advanced node wafer orders may be 1-2 years in advance, and that process flow durations are layers/complexity dependent, and can range from a couple months to more than a few months.
But I trust SemiWiki answers much more than elsewhere.
It could be
1. To sell chips manufactured in advanced nodes, it takes time to validate design and applications, which might take months or 1-2 years in preparation.
2. If no wait and wafers can be started when put order, then you can estimate the cycle time of wafer out by masking layers x days/mask. For example, if your process needs 70
masking layers, then it will take ~70x2=140 days roughly. If you pay for hot lot, then the wafer out can be earlier. This is wafer process time, not including packaging and tests.
Fwiw Pat Gelsingers predecessor negotiated TSMC N3 wafer allocation, years ago. Pat became CEO Feb 2021.
How far ahead does capacity have to be secured versus how far ahead does fabless need to get wafers versus how long does it take to bring a new node are very different.
As to real time from wafer starts to into the hands of a consumer.
Figure 3 months for fab processing
Figure 1 month for OSAT
Figure 1-2 months for final product
Figure 1-2 months for distribution
So 6-9 months from starts to BestBuy
From TI to fab out don’t forget you have OPC computation plus mask making can be 2-4 weeks than fab time assume 1DPML as a base line so figure three months for first A step. Don’t forget after fab out expedite for assembly. Beyond this there is a ton of early work and short loops that must be done in fab and OSAT for the new product as the die size and layout have never been run or targeted. Also after first silicon is out the whole test must be optimized before functionally at package and final product can happen.
The whole getting read for new node is even bigger.
As to when whale signs up for capacity that is years sometimes before the node is ready and the first production fab is built.
Think of the cycle time for fab and think about designing IP and characterizing it all over several fab cycles and than final validation and than design and incorporation into the first A step. Let’s not get into the part of A step doesn’t work and you need debug and design respin for either metal or worse base layers.
As to real time from wafer starts to into the hands of a consumer.
Figure 3 months for fab processing
Figure 1 month for OSAT
Figure 1-2 months for final product
Figure 1-2 months for distribution
So 6-9 months from starts to BestBuy
From TI to fab out don’t forget you have OPC computation plus mask making can be 2-4 weeks than fab time assume 1DPML as a base line so figure three months for first A step. Don’t forget after fab out expedite for assembly. Beyond this there is a ton of early work and short loops that must be done in fab and OSAT for the new product as the die size and layout have never been run or targeted. Also after first silicon is out the whole test must be optimized before functionally at package and final product can happen.
The whole getting read for new node is even bigger.
As to when whale signs up for capacity that is years sometimes before the node is ready and the first production fab is built.
Think of the cycle time for fab and think about designing IP and characterizing it all over several fab cycles and than final validation and than design and incorporation into the first A step. Let’s not get into the part of A step doesn’t work and you need debug and design respin for either metal or worse base layers.
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Fab time is significantly longer than 3 months for advanced nodes...
fansink
Active member
Almost a year -- but that wasn't TSMC... ;-)
MKWVentures
Moderator
Couple items to separate:
1) capacity allocation . this is what Intel and Apple and nvidia request... guaranteed capacity. Take or pay on the contract or prepay. years in advance
2) Lead time for orders once product qualified. depends on loadings..... could be cycle time (no delay in start) or 6+months. typically there are forecasts and adjustments to forecasts.
3) Cycle time: for fab is is around 4 months.
4) Once you are running volume, the inventory at customer and in process at TSMC starts to play a role.
In between all of this is lots of negotiation on pricing and delivery to keep factory loaded and efficient and minimize end inventory. TSMC is VERY good at this.
1) capacity allocation . this is what Intel and Apple and nvidia request... guaranteed capacity. Take or pay on the contract or prepay. years in advance
2) Lead time for orders once product qualified. depends on loadings..... could be cycle time (no delay in start) or 6+months. typically there are forecasts and adjustments to forecasts.
3) Cycle time: for fab is is around 4 months.
4) Once you are running volume, the inventory at customer and in process at TSMC starts to play a role.
In between all of this is lots of negotiation on pricing and delivery to keep factory loaded and efficient and minimize end inventory. TSMC is VERY good at this.
C.C Wei said
"we set the pricing of N3 very early, several years ahead of production. However, we experienced a lot of cost inflation pressures in the following years. So as a result, N3 will take a longer time than N5 and N7 to reach the corporate average gross margin."
How come TSMC can not raise the price of 3nm later?
When will we see TSMC raise 3nm price?
"we set the pricing of N3 very early, several years ahead of production. However, we experienced a lot of cost inflation pressures in the following years. So as a result, N3 will take a longer time than N5 and N7 to reach the corporate average gross margin."
How come TSMC can not raise the price of 3nm later?
When will we see TSMC raise 3nm price?
MKWVentures
Moderator
@Daniel Nenni
Does TSMC really set the pricing that early? there are no adjustments? I do know the pricing varies A LOT by customer. a low volume/variable customer will pay 2x the price of a high volume customer.
Does TSMC really set the pricing that early? there are no adjustments? I do know the pricing varies A LOT by customer. a low volume/variable customer will pay 2x the price of a high volume customer.
Mooredaddy
Well-known member
I was pretty shocked and disappointed by this. I know TSMC harps on “pricing strategically” but it really feels like they aren’t extracting their pound of flesh like they should from their leadership. They surely know better then all of us, especially me, but it is concerning they didn’t price N3 to capture projected value and costs.
Not surprise to me. I would say this could depend on the business situation. There are very few customers can afford 3nm technology and as the early adopter, the one definitely will ask for the price very early based off the previous nodes, its cost structure and more. As we know, dimension shrink ere was gone and it becomes very tricky to validate chip price based on performance and leakage improvement, when chip unit price increased. What CC told us implied 3nm structure cost reduction speed did not meet 5nm or 7nm trend in TSMC. If keep the same wafer price, I will expect the competition barrier (wafer cost, fab profitability) will keep high for the catch-up foundry (intel and Samsung).
When you are the leader and need to invest billions a year in RD as well as tens of billion in manufacturing capacity you make assumptions on Yield, tooling cost and all other things years ahead and than negotiate wafer price with your customers.
Situation four years ago, a year ago and now the market conditions for demand as well as cost of the tools, chemicals have changed a lot.
I am surprised that TSMC doesn’t have pricing like UBER does. They are the only supplier. You’d think they would be savy enough to extract more margin out of the AI companies. The risk they take and capital they have to invest pales compared to the fabless. Just look at Intels long road to profitability it is on to the fixed cost that is sunk before you get profit
Situation four years ago, a year ago and now the market conditions for demand as well as cost of the tools, chemicals have changed a lot.
I am surprised that TSMC doesn’t have pricing like UBER does. They are the only supplier. You’d think they would be savy enough to extract more margin out of the AI companies. The risk they take and capital they have to invest pales compared to the fabless. Just look at Intels long road to profitability it is on to the fixed cost that is sunk before you get profit
Generally, it depends on masking layers and also how much you pay for delivery. If you pay for hot run with 80 masking layers, then you might get wafers less than 3 months.
For the big customers, pricing and delivery is set by the wafer agreement that is signed before the design even starts. Quite a few customers have to pre pay to play now with TSMC dominating the leading edge. Intel had a HUGE pre pay I am told, a very different agreement than other pre payers. CC Wei does know how to negotiate. I saw CC Wei at the Symposium today but he did not speak.