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Transistor-level Sizing Optimization

Transistor-level Sizing Optimization
by Daniel Payne on 08-29-2014 at 4:00 pm

RTL designers know that their code gets transformed into gates and cells by using a logic synthesis tool, however these gates and cells are further comprised of transistors and sometimes you really need to optimize the transistor sizing to reach power, performance and area goals. I’ve done transistor-level IC design before,… Read More


IO Design Optimization Flow for Reliability in 28nm

IO Design Optimization Flow for Reliability in 28nm
by Daniel Payne on 07-31-2014 at 5:00 pm

User group meetings are a rich source of information for IC designers because they have actual designers talking about how they used EDA tools in their methodology to achieve a goal. Engineers at STMicroelectronicspresented at a MunEDAUser Group on the topic: I/O Design Optimization Flow For Reliability In Advanced CMOS Nodes.… Read More


Five Things You Don’t Know About MunEDA

Five Things You Don’t Know About MunEDA
by Paul McLellan on 06-17-2014 at 3:00 pm

So first the one thing that you do know. MunEDA are based in Munich which makes them German. I have to confess that until I got involved helping them a bit with some marketing stuff that that was about all I knew about them too.

So now five things that you might not know:

1. MunEDA have a much wider customer list that you know and would even… Read More


High Sigma Yield Analysis and Optimization at DAC

High Sigma Yield Analysis and Optimization at DAC
by Daniel Payne on 06-02-2014 at 7:20 pm

When I hear the phrase “high sigma” I think of the EDA vendor Solido, however at DAC on Monday I visited another EDA company called MunEDAthat has several products of interest to transistor-level IC designers. I was able to speak with three different people from MunEDA and here’s what I learned.

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Full-Custom Low Power Design Methodology

Full-Custom Low Power Design Methodology
by Daniel Payne on 05-19-2014 at 1:30 pm

Digital designers have used logic optimization and logic synthesis for decades as a means to produce more optimal designs with EDA tools. On the analog and transistor-level side of design the efforts to automatically optimize for speed or power have generally been limited to circuits with only a handful of transistors. These … Read More


Low Power Design

Low Power Design
by Paul McLellan on 05-16-2014 at 9:08 pm

So you want to do a low power design. Join the club. Who doesn’t? Today all designs are low power, it is the biggest constraint on what we can do on a chip. Power down; power domains, variable clock rates, mixed Vt libraries. Every trick is needed. And that is not even enough. We get to put our phones on charge each evening and there… Read More


A Brief History of MunEDA

A Brief History of MunEDA
by Paul McLellan on 05-12-2014 at 4:56 pm

In 2002, MunEDA was launched under the guidance of EDA academic veterans and IEEE fellows Prof. Kurt Antreich and Prof. Helmut Gräb (TUM Munich Technical University ) which represented 20 plus years of EDA research and experience. All MunEDA tools are combined in a tool suite called WiCkeD[SUP]TM[/SUP]. The tool suite brand was… Read More