Reusing design IP is crucial for competitiveness. The need for reuse occurs with new designs on the same process node as the original design, new designs at the same node but using a different PDK or foundry, or designs on a different process node – usually smaller. However, achieving effective IP reuse has always been a challenge.
Digital designs are often expressed in an HDL such as Verilog or VHDL. Because of the design flow used for HDL based designs, recreating gate level representations targeted at different libraries and process nodes is manageable. However, when it comes to AMS, full custom or RF designs, porting to new technologies becomes a much more difficult proposition.
These designs are most often represented with schematics. When switching to a new PDK, designers will need to convert the schematic so that it uses the cells available in the new library. Not only can the cell/symbol name change but there will be changes in the number and names of the pins, and more fundamentally there will be changes in design parameters that determine circuit performance. Probably no design task is more tedious and risky than manually porting a schematic.
I’ve written previously about MunEDA’s circuit optimization software, but they also have expertise in schematic porting. According to MunEDA, the challenges of schematic migration are:
- Different device parameters (vth, etc.) require adjustment of biasing and small signal parameters
- Needed W, L shrinking is not as simple as digital
- Some devices (mimcaps, inductors, etc.) may or may not be available, or may be of a different type
- Circuit topology may need modification
- Layout shrinking in integrated technologies is insufficient
MunEDA suggests a 3 step process starting with updating the schematic with the new library symbols. As previously mentioned this is complicated by new symbol names, potentially different number of pins, and changes in parameter names. MunEDA offers their Schematic Porting Tool (SPT) that can significantly automate this process.
Once the symbol mapping information is entered for the two libraries, MunEDA SPT can replace 100’s or 1,000’s of symbols in seconds. MunEDA’s SPT is fully integrated into Cadence Virtuoso based custom and analog design flows. This includes properly handling SKILL context files, wrapper scripts and configuration scripts. The error prone manual alternative would take orders of magnitude longer. Here are some examples of the operations that SPT can perform.
The second step of the MunEDA flow involves assessment and topology changes in the schematic to accommodate the new PDK. Any desired topology changes can be made at this point to accommodate the new library. Once this is done, the design is ready for automated sizing and optimization.
The last and most important step is modification of the design parameters so the circuit operates properly. MunEDA SPT lets users create their own sizing strategy. It also supports multi-objective optimization, including power and noise minimization. Sizing can also can be done over multiple process corners.
The MunEDA website offers several papers on use of SPT by their customers, including examples submitted by the University of Dresden, STARC, Evatronix and others. Look here for the specifics.
Despite the usual difficulty automating custom, analog and RF design steps, it’s good to know there are options for dramatically improving the process of porting schematics to new PDK’s. MunEDA is able to do this by building on their clearly established expertise in custom circuit design optimization.