Taking a leap forward from TCAD

We all know that Technology Computer Aided Design (TCAD) simulations are essential in developing processes for semiconductor manufacturing. From the very nature of these simulations (involving physical structure and corresponding electrical characteristics of a transistor or device), they are predominantly finite-element based simulations with complex set of equations to be solved which require large computation, thus increasing simulation time exponentially with the size of the device. It was okay for earlier generations of semiconductor technology nodes to rely on transistor or small cell level process and characterization to develop large designs which were then verified through several build-and-test cycles through actual foundries. However, for today’s nanometer technology nodes and large, complex, high-density designs with complex transistor structures like FinFET and others which exhibit excessive variability in manufacturing, it’s clear that the same old methodology will no longer be effective. . Along with the technology, the economics of chip manufacturing and marketing has become equally pressing, needing substantial reduction in P/Q ratio and very high TAT in order take advantage of ever shrinking windows of opportunity.

TCAD simulations still have to be done to accurately develop the process and model a semiconductor device, but the challenge is to scale that to model today’s large semiconductor designs with the same level of accuracy such that they can be correct by construction and manufactured without any fault. Although I have been writing about the novel concept of Virtual Fabrication Platform provided by Coventorthrough its set of tools in SEMulator3D – which provides a detailed 3D modeling capability for any semiconductor design to enhance accuracy, reduce variability and improve yield,- my belief is further strengthened after reading this blogwritten by Mike Hargrove.

Mike reveals that the process modeling platform of Coventor combines with the statistical device TCAD suite of tools from Gold Standard Simulations Ltd. (GSS), an innovative company led by the Device Modeling Group in the University of Glasgow that provides physical accuracy, efficiency and usability in true sense. What scales this device modeling of real gold level standard to large designs is the voxel-based mesh, very fast and efficient computational engine and several other features of SEMulator3D such as ‘Structure Search’, ‘Layout-Aware Rebuild’, Expeditor and other Etch processes about which we have talked in the past.

The above 16nm FinFET SRAM half-cell model built in SEMulator3D in less than an hour is a result of the collaboration between Coventor and GSS. Add to it just a few hours of additional Fin profile variation simulations. A complete design block can be modeled and simulated to perfection before sending it into the actual foundry, thus saving huge money and time spent in build-and-test through fab.

The SEMulator3D can output tetrahedral meshes which can be easily imported into standard TCAD tools. In the above image, a tetrahedral mesh is shown along with individual pull-up (PU), pull-down (PD) and pass-gate (PG) transistors for single transistor simulation studies. Advanced studies such as the effect of Fin profile (which involves multiple process parameters) on individual transistor performance can be done with ease.

The PU and PD devices were simulated using GSS’s TCAD tool Garand. The important electrical characteristics such as the hole-density profile of a PU device can be studied to optimize the device performance.

It’s interesting to know that today we do have a solution that doesn’t require expensive in-fab experiments to choose the best technology option to model a particular large semiconductor design; accurately as per desired electrical characteristic, with improved yield and reliability, and reduced variability. This significantly reduces the design risk with the kind of advanced and complex technology nodes we have today, and at an ‘order of magnitude’ reduced cost.

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