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May 29, 2020January 21, 2021

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs

Minimizing Power Consumption in Ultra Low Power MCU Based SoCs
by Tom Simon on 05-29-2020 at 6:00 am
Categories: Dolphin Design, EDA, IoT, IP, Mobile

When it comes to extremely power sensitive applications such as IoT and edge devices, there is literally an arsenal of power saving techniques that could be used. The tricky part is figuring out which ones to use and how to use them for maximum benefit. This is coupled with the need to not hamper device performance or functionality. The trend is for increasing use of Ultra Low Power 32-bit microcontrollers (ULP MCUs) in SOCs for devices such as industrial instrumentation solutions, industrial controllers, connected home consoles, thermostats, temperature sensors, smart meters, smart grids, blood glucose meters, heart rate monitors, implantable devices, and IoT devices.

The range of possible power reduction techniques go from device and cell level to block and chip level, including mixed Vth cells, body biasing, thick oxides, clock gating, power gating, frequency scaling, always on domains, etc. Some of these techniques can be applied once during design and can be ‘forgotten’. Others need intelligence of their own to help manage them in conjunction with chip operation. Dolphin Design has recently published a white paper that does a good job of reviewing traditional and new power management techniques and discussing how they can and should be applied. The paper is titled “Breaking new energy efficiency records with advanced power management platform. “

Dolphin Design cites reports that show the ULP MCU market growing from $4.4B to $12.9B from 2019 to 2024. Many of these ULP MCUs will support analog mixed signal IoT devices that will have very complex operation modes and need to operate for weeks, months or years on a single batter or charge.

The white paper takes a look at various methods of power management, starting with off-chip PMICs, then progressing to on-chip Power Management Units (PMU) and programmable PMUs. Moving from a discrete PMIC to an on-chip power management approach reduces the BOM and permits tighter integration of power management functions. One drawback of on-chip software based power management is that the processor needs be ‘always-on’ which makes it a power sink, especially for chips that spend significant time in sleep modes. The alternative is to design FSM based logic that can provide most of the functions needed for power management, with reduced power consumption. Yet, FSM based PMUs are not as flexible

Dolphin Design describes their comprehensive power management solution Spider in their white paper. Their approach uses a power controller called MAESTRO, which is fully configurable IP that works like a state machine, but can but reprogrammed in the field if desired.

But there is a lot more to it. Dolphin Design have a comprehensive set of regulator IP that are extremely efficient at converting battery and supply voltages to on-chip logic levels. They are configurable as well, providing flexibility. Dolphin Design talks about their ultra-low leakage IP that are used for the always-on blocks. These include LDOs, dedicated oscillators and power gating solutions. The white paper also mentions PowerStudio, their GUI for configuring and controlling their low power elements. PowerStudio helps to verify the power management system as well. It offers a wide range of checks that cover power mode transitions, ICU responses, power mode coverage, ICU states, regulator model consistency, isolation, isolation control and retention.

The last portion of the white paper talks about benchmarking power consumption and efficiency. ULPMark-CoreProfile (ULPMark-CP) considers leakage current in sleep modes and active mode power consumption. Unlike peripheral power usage, MCU power varies significantly depending on the efficiency of the power management techniques that have been applied. Dolphin Design offers detailed results of benchmarking that compares the approaches mentioned above. From the baseline external PMIC to full utilization of all the methods that Dolphin Design supports there is a 2 orders of magnitude improvement of the ULPMark-CP numbers.

The Dolphin Spider platform promises to be extremely useful and efficient for the needs of ULP MCU designs. There is no doubt that the need for more efficient and longer life battery-based devices will continue to expand. Eliminating unneeded power consumption is the most cost-effective way to meet these market requirements. The full white paper is available on the Dolphin Design website and makes interesting reading on how a comprehensive power management system can deliver impressive results.

May 28, 2020October 3, 2020

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support

PLDA Expands Data Interconnect IP Solutions with CXL and Gen-Z Protocol Support
by Mike Gianfagna on 05-28-2020 at 10:00 am
Categories: IP, PLDA

A couple of months ago I introduced PLDA, a new member of the SemiWiki community, with a post about PLDA’s switch IP and its support for PCIe and NVMe solid state disks. Working in the area of high-performance data interconnects requires support for a growing list of standards, standards that continually evolve. The trick is to stay at the leading edge of these standards so support is available early in the design process.

A recent press release from PLDA illustrates the company’s commitment to emerging standards. Entitled PLDA Announce Complete Support for CXL™ and Gen-Z™ protocols, the announcement has a back-story worth mentioning.

First, let’s look at the CXL protocol. Compute Express Link (CXL) is a new high-speed interconnect specification that focuses on CPU-to-device and CPU-to-memory applications. The technology maintains memory coherency between the CPU memory space and memory on attached devices, which improves performance and lowers complexity and cost. The spec is being developed by an open industry standard group formed by some very prestigious companies.

Gen-Z is a new data-access technology that offers low-latency for data and devices through direct-attached, switched or fabric topologies. Gen-Z fabrics utilize memory-semantic communications to move data, which minimizes overhead. Gen-Z is also developed by an industry consortium that has its own A-list members. Some of you may be wondering what memory-semantic communications is. The consortium posted this on Twitter to help: “What is memory semantic fabric? Communication at the speed of memory. A comm protocol that speaks the same language the CPU speaks”.

The goal of standards like CXL and Gen-Z is to enhance communication between compute and main memory to support more complex storage structures within and across systems. For further reading, this article sums it up as follows: “It will be hard to tell the difference between a system and a cluster … where there are memory servers, compute servers, and storage servers, all glued with a Gen-Z fabric into a very memory centric cluster.” Looking at the two standards, there is no Gen-Z without CXL. As these standards are deployed, Gen-Z will be bridged to CXL to extend CPU reach beyond the compute node, in composable data centers for rack/row/long-haul communication. Gen-Z expected to replace Infiniband in this scenario.

There’s one more important development to mention. On April 2, 2020, the CXL Consortium and the Gen-Z Consortium announced a memorandum of understanding. In an ecosystem that is characterized by highly competitive and secretive behavior, it is noteworthy that these two organizations decided to collaborate for the greater good. As stated in the announcement, “The MOU outlines the formation of common workgroups between both organizations to provide clear cooperation, defining bridging between the protocols while leveraging the strengths of both technologies.”

It is against this backdrop that the recent PLDA press release was made. Thanks to the clarifications provided by the MOU, PLDA is committed to support both protocols, with a focus on CXL IP first.

XpressLINK CXL is a parameterizable soft IP controller designed for both ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA’s silicon-proven XpressRICH Controller for PCIe 5.0 architectures. The IP includes:

Support for the CXL 2.0 specification
Implementation of the CXL.io, CXL.mem, and CXL.cache protocols
Support for all three defined CXL device types
Support for the PCI Express 5.0 Base Specification, Revision 1.0
Support for the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface widths

Regarding availability, PLDA’s current XpressLINK CXL roadmap extends from the second half of 2019 to the first half of 2021. This aligns well with the roadmap of processor vendors like Intel. PLDA is already engaged with early adopters for this technology.

“The announcement of the MoU between the CXL and GenZ Consortiums is a key event in the IP Market as it paves the way to the future architecture of high speed interfaces,” said Arnaud Schleich, CEO of PLDA. “As an historic actor in this Industry, it was logical for PLDA to expand its product line to include both protocols and we are proud to be committed to pushing this evolution to the next level.”

Gen-Z early silicon is not expected before the second half of 2022. As stated by Gen-Z Consortium Chairman Kurtis Bowman in April 2020: “… Gen-Z early adopters will be coming online in 2022 and it will be mainstream by 2023 to 2024….”). PLDA’s roadmap for Gen-Z IP begins in 2021, but the company already demonstrated a proof of concept of their Gen-Z at SuperComputing 2019.

Supporting two emerging, complex protocols at the leading edge is not easy. PLDA appears to have done a great job here. For more information on this new standards-based IP, you can visit PLDA’s CXL IP webpage or PLDA’s Gen-Z IP webpage.

May 28, 2020August 25, 2020

What a Difference an Architecture Makes: Optimizing AI for IoT

What a Difference an Architecture Makes: Optimizing AI for IoT
by Bernard Murphy on 05-28-2020 at 6:00 am
Categories: AI, EDA, Siemens EDA

Last week Mentor hosted a virtual event on designing an AI accelerator with HLS, integrating it together with an Arm Corstone SSE-200 platform and characterizing/optimizing for performance and power. Though in some ways a recap of earlier presentations, there were some added insights in this session, particularly in characterizing various architecture options.

Accelerator Design

Mike Fingeroff kicked off with high-level design for the accelerator, showing a progression from a naïve implementation of a 2d image convolution with supporting functions (eg pooling, RELU) in software. This delivered 14 seconds per inference where the final goal was 1 second. His first goal was to unroll loops and pipeline. New here (to me at least) is that Catapult generates a GANTT chart, giving a nice schedule view to guide optimization. So Mike unrolls and finds he has memory bottlenecks, also highlighted by a Silexica analysis. Not surprising since he’s using a 1-port memory, again with naïve reads and writes. He switches to a shift-register and line-buffer architecture supporting a 3×3 sliding window in convolution and the bottleneck problem is solved. He also looks at Silexica analyses to decide how/if to buffer weights. Now he’s down to just over a second per inference with bias, RELU and pooling still in software (running on the embedded CPU).

Then he runs Matchlib simulations for a more comprehensive analysis (couple of hours) and find some outliers, such as one inference taking 4 minutes, principally caused by delays in CPU computations. He pushes these software functions into the hardware (which adds little overhead) and that problem goes away. While he’s met the performance goal, Mike also talks briefly about ways to further increase performance, through added output parallelism (compute 2 outputs per cycle) and input parallelism (fetch and compute on 2 inputs per cycle since the input bus is 64bit and he only wants 32bit accuracy in the inference).

Arm subsystem integration

Korbus Marneweck from Arm followed, introducing Arm IoT solutions with Corstone (the Mentor demo is integrated into this platform). Corstone provide reference designs for secure IoT implementation, with TrustZone, security IP and lots of other goodies and setup for an easy path for PSA certification. There’s quite a lot more detail on Corstone which I’ll skip in the interest of quick read. Korbus did talk about method to connect an accelerator, through a memory-mapped path, as a co-processor or through custom instructions. That raised some Q&A on working with custom instructions which may be interesting if you want to dig deeper into the video.

Characterization

Russ Klein took the last part of the presentation, talking about integrating this all together and especially characterizing for performance, area power/energy per inference. This for me was the most interesting part of the talk because it puts hard numbers behind the benefits of an HLS-based approach to designing these AI accelerators. Quick clarification here, they measured characteristics just for the implemented accelerator, not the Corstone subsystem. However within the accelerator they are running full implementation (based on Mentor tools) and using parasitics from that implementation. The table opening this blog shows the results.

The first row is for a very naïve software-only implementation using floating point. That’s just a reference for grins. The second uses integers rather than floating point, delivering ~10 minutes/inference at ~5 joules/inference. First pass unoptimized CNN plummets to ~50 seconds and 800mW/inference. Windowing (shift registers and line-buffers) drops to 9 seconds and 135mJ/inference. Analysis continues through various combinations: parallel out, moving the RELU etc. functions into the kernel and parallel in, until they get down to 8-bit data running through a quad convolver deliver a quarter second and 6mJ per inference. That’s a lot of architecture options they explored, all enabled by starting with an HLS model and looking at tradeoffs in pipelining, windowing, memory architectures and input and output parallelism. None of that feasible on the network model side (which doesn’t understand hardware constraints and options) or on the RTL side (which would be impossibly painful to keep rearchitecting.

Good stuff.

You can check out more on this topic through Mentor’s on-demand webinars. See for example their webinar on sliding window memory architecture for performance.

May 27, 2020September 30, 2020

The Growing Relevance of IP-XACT in Today’s Complex Designs

The Growing Relevance of IP-XACT in Today’s Complex Designs
by Ranjit Adhikary on 05-27-2020 at 10:00 am
Categories: EDA, Magillem

The life of a SoC designer is an unenviable one. Not only does he have to work in a landscape where competition is intense but he also has to collaborate effectively with globally dispersed teams to ensure the design meets the project timeline. Then there are also the risks, more so in the current pandemic! There is the constant fear of a dead chip on arrival or issues found post silicon or the tape-out slipping beyond the due date which can have widespread ramifications. As part of a multi-pronged strategy to mitigate the risks as well as build designs faster, a large number of companies have slowly but steadily moved towards using verified third-party IPs, for parts of the design which is not in their core competency.

However, this trend of incorporating more and more third-party IPs in an SoC is not without its share of problems. The complexity of IP configurations now is no longer easy to manage manually and requires an infrastructure which is capable of tracking the configurations throughout the product life cycle. The tight marriage required between the hardware and software teams to provide state-of-the-art SoCs of today adds yet another dimension to the challenges faced by the designers. The need for a methodology to build, update and configure IPs appropriately is felt more so than ever. While there are some software solutions which address this aspect of the problem to some extent, their reliance on proprietary technologies and inability to coexist with legacy flows poses a problem for a large number of companies.

Over the last half decade, companies have slowly embarked on an effort to addressing these issues and automating flows while relying on standards as an underlying infrastructure and ensuring a common data-model which can be leveraged between all the teams.

It is no mere coincidence that most enterprises have chosen IP-XACT as the underlying standard to base their infrastructure for developing automated flows.

What is IP-XACT?

IP-XACT, first released by the SPIRIT Consortium, is a standard developed with the sole objective of promoting reusability of IPs within the design community. It enables IP providers to provide a singular description of their IPs which is both readable and machine processable for both components and designs, and share it with the IP users packaged along with the desired collateral. IP-XACT also describes system designs and the interconnection between the IPs along with other details such as address maps, interfaces etc. providing a common design representation that can be used by IP vendors, design integrators and EDA tool providers to exchange within their flows.

IP-XACT became an IEEE standard in 2009 and is published as IEEE-1685. While a number of companies started using it even before it became an IEEE standard, the usage started increasing in the last few years as more and more companies realized the potential it offered in helping create and automate their custom design flows.

Why the sudden increase of interest in IP-XACT?

With a lot riding on the SoCs of today, both small and large semiconductor companies alike, are heavily invested in the common goal of ensuring successful tape-outs within the scheduled timelines. Any delays or snags in the design flow can potentially impact both their time-to-market as well as the company bottom line.

Most design teams have attempted to resolve this issue by working in parallel on several fronts and investing heavily on block and system-level verification. For example, top level and block level design integration of designs is done in parallel to the development of RTL and verification environment. But this approach is not the most optimal often requiring more resources and prone to manual errors.

Another issue which designers face involves the EDA tools produced by a number of vendors, many of which use unique and proprietary formats. Developers are often posed with the problem of identifying ways to exchange the design information efficiently between different design environments.

One way to resolve this and ensure timely and successful tape-outs is to provide for a solution, which encompasses at the very least:

A well-defined design methodology suited for your custom requirements and EDA tools of your choice
Efficient design collaboration between design teams sometimes dispersed across geographical boundaries especially between hardware & software teams
Leverage IP reuse for internal and third-party IPs
Design flow automation which ensures
- Faster design integration
- Selecting the correct configuration of IPs
- Smooth exchange of design information between different tools and ensuring design handoffs between teams
- Avoiding misinterpretation of design specifications such as register maps
- Automatic generation of RTL and other collateral such as C header files, memory maps, UVM models, documentation etc.

In the past, companies have tried to address some of these problems, by creating solutions based on either custom scripts, proprietary technology or a combination of both. The challenge with this approach has been that the solution needs to be constantly maintained and tends to fall apart when the engineers managing the solution leave the company. The ability to integrate design flows by creating custom generators to pilot EDA tools and back annotate the results has resulted in companies now taking a hard second look at IP-XACT to serve as the underlying vehicle for their tooling solutions. IP-XACT stands out in being an IEEE standard, which means that companies no longer have to worry about maintaining or enhancing any proprietary infrastructure. By providing a standardized data exchange format, IP-XACT has the flexibility to represent multiple companies’ requirements and the hooks to allow design information to be automatically extracted and used in flow automation and advanced verification.

One of the important cornerstones of the IP-XACT standard is its capability of packaging a design into an IP-XACT component. The component description includes among other things, the specification of the periphery of each IP block along with the bus interfaces, physical signals, their mapping to logical bus interfaces, configuration, address blocks, register descriptions, filesets and documentation information. The information contained in the description can be used by designers to automatically integrate the correct configuration of IPs and construct the SoC faster in a single integrated design and verification environment while mitigating the possibility of any errors being introduced in the design.

An inherent advantage of using IP-XACT is that it not only helps in improving the IP ecosystem within a company as design teams can easily package a design along with the necessary collateral, but its use as a common data model also enables distributed teams to collaborate more efficiently and exchange design information quickly between different design environments. IP-XACT also comes equipped with a standard API which can be used to customize solutions even further by complimenting the IP-XACT description with a layer of software. For example, the API could be used with an EDA tool to actually interface into a customer flow by leveraging the design information available in the IP-XACT database. Using the API, embellishes the value proposition of the generators and can be used to capture the configuration intelligence within the generators to automatically generate the final configured IP-XACT description of an IP. This capability is of immense value to an IP provider as it enables a precise and controlled use of the selected configuration.

The versatility of the IP-XACT standard and its ability to coexist and work with other systems including legacy ones used for IP reuse and flow integration, makes it the perfect choice for many a company.

Advantages of using IP-XACT

One of the most important aspects of IP-XACT is that it is an IEEE standard backed by leading semiconductor companies who are heavily invested in utilizing it for tooling purposes as well as IP reuse. The fact that it is developed keeping IP reuse in mind, makes it ideal to build IP ecosystems within an enterprise.

Design teams can leverage this ecosystem by using it to create more IP sub-systems and SoCs. To assemble the designs faster, designers can use the connectivity features defined in IP-XACT to quickly create an interconnect fabric for their designs and utilize the register maps of the IPs to compute the full system memory map of the design. Designers can also use the design database to create generators such as s/w C header files, netlist in VHDL, Verilog, System Verilog or System C, UVM models, testbenches, documentation etc.

One of the lesser known advantages of IP-XACT and one of the most important capabilities is that it can be used extensively for tooling purposes and automating the flows, something which a number of companies have started to capitalize on of late.

Some of the other capabilities which IP-XACT possesses includes

IP-XACT is designed for IP reuse
Faster and easier system integration
- Support for multiple layers of abstractions (designs and protocols) enables integrators to quickly create the top level for the designs.
- Built in error checks reduces the possibility of errors
Extensibility to add design and flow information
With support for features such as views/fileSets,, managing deliverables becomes simple and fully automated process.
Support for design traceability which is a key requirement for ISO 26262 certification

A standard does not have to be perfect but if there are enough people adopting it over time, it can be considered to be a good standard. This applies to IP-XACT as well. With the number of companies adopting the standard increasing steadily, there is no doubt that the standard is here to stay.

Finding the right solutions

To hasten the process of developing the SoC or IP, it becomes necessary to use solutions which are tried and tested and is part of a production flow in several companies. For more information on how to build your designs faster, visit www.magillem.com. Magillem customers include the top 20 semiconductor companies worldwide.

Magillem is a pioneer and the leading provider of IP-XACT based solutions aimed at providing disruptive solutions by integrating specifications, designs & documentation for the semiconductors industry. Using the solutions provided by Magillem, design companies can automate their design flows and successfully tape-out their designs faster at a reduced cost.

It is one of the leading authorities on IP-XACT standard. Magillem is the Co-chair of the IP-XACT 2021 Accellera committee and an active member since the inception of the IP-XACT standard.

May 27, 2020May 4, 2022

Is the Worst Over for Semiconductors?

Is the Worst Over for Semiconductors?
by Bill Jewell on 05-27-2020 at 6:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The worldwide economic outlook is chaotic due to the ongoing COVID-19 pandemic. The outlook for the semiconductor market is also very uncertain. 1Q 2020 revenue versus 4Q 2019 was mixed for major semiconductor companies, ranging from a 19% decline for STMicroelectronics to 9.9% growth from Kioxia (previously Toshiba Semiconductor). WSTS reported a decline of 3.5% for the semiconductor market in 1Q 2020. Guidance for 2Q 2020 revenues shows continued caution. Most companies expect a decline in 2Q 2020 revenues from 1Q 2020.

The range of 2Q 2020 guidance is wide. Low end 2Q 2020 guidance from Qualcomm, Texas Instruments, STMicroelectronics and NXP Semiconductors ranges from -14% to -22%. The upper end guidance for these companies ranges from -7% to -0.3% and the midpoint guidance averages -10.5%. Seemingly optimistic guidance from Nvidia and Infineon is deceptive. Nvidia began to include the revenue of its Mellanox acquisition in 2Q 2020. Excluding the effect of the Mellanox acquisition, the midpoint of Nvidia’s 2Q 2020 guidance would be about 4% instead of 18.5%. Similarly, Infineon is including revenue from its Cypress Semiconductor acquisition in 2Q 2020. Excluding Cypress, the midpoint of Infineon’s guidance would be about -13% instead of +5.7%.

The memory companies (Samsung, SK Hynix, Micron and Kioxia) generally had positive 1Q 2020 revenue growth compared to 4Q 2019. The midpoint of Micron’s guidance for its fiscal quarter ending later this month is +2.1%. Samsung, SK Hynix and Kioxia did not provide revenue guidance for 2Q 2020, but they all expect strong demand from PCs and servers but declining demand from smartphones.

PC demand is expected to be strong as many more people are working from home or receiving educational instruction from home. Increased dependence on the internet for communication and information is driving continued growth in servers for data centers. IDC in March forecast a 9% decline in PC and tablet unit shipments in 2020 based on weakness in the first half of the year and a pickup in the second half. IDC reported 1Q 2020 PC unit shipments declined 9.8% from a year ago, following three quarters of year-to-year growth in 2019.

Smartphone demand in 2020 is more uncertain. IDC in March forecasted a 2.2% decline in smartphone unit shipments for the year. In April, Strategy Analytics projected a 23% decline. IDC reported 1Q 2020 smartphone unit shipments were down 11.7% from a year ago. Although many experts expect weak smartphone demand in 2020, sales could be driven by increased use of video communication. Just as businesses are using video conferencing on PCs to increase communication among remote employees, households are increasingly using video over smartphones to communicate with family and friends they cannot visit in person. This increased use of video may prompt many to upgrade their smartphones.

1st quarter 2020 electronics declines were primarily due to supply issues. China electronics production was down significantly in January and February as China shut down much of the country in an effort to contain COVID-19. January and February 2020 China electronics production value in yuan was down 13.8% from a year ago. Unit production of PCs was down 29% and mobile phone unit production was down 41%. China production value has since recovered, with March up 9.9% from a year ago and April up 11.8%. PC unit production was up 29% in April versus a year ago. Mobile phone unit production has yet to return to previous levels, with April down 26% from a year ago.

Electronics markets for the remainder of 2020 will be driven by demand. For the second quarter, most of the world was under stay-at-home orders (or recommendations) for the month of April. Many countries are beginning to open up in May and continuing into June. Economic activity should continue to pick up in 3Q 2020 and 4Q 2020 barring a significant reemergence of COVID-19. 2021 should be a strong growth year as the economy returns closer to normal and pent-up demand drives increased spending by consumers and businesses.

Recent forecasts for the semiconductor market in 2020 vary widely, as can be expected. The highest forecast is 7.6% growth from the Cowan LRA model. The Cowan model is based on historical trends and does not take into account current events such as COVID-19. Omdia expects 2.5% growth. Gartner expects a decline of only 0.9%. McKinsey calls for a decline of 5% to 15% (with a -10% midpoint). IBS is the most pessimistic at an 11.7% decline. IC Insights and IDC each project a decline of about 4%. Our latest forecast from Semiconductor Intelligence is a 6% decline in 2020.

The memory market remains the one bright spot in the semiconductor market in 2020. Gartner expects memory to grow 14%. Gartner forecast a 6% decline in semiconductors excluding memory, compared to a 0.9% decline for total semiconductors. Omdia also see memory driving grow, with its 2.5% growth forecast for semiconductors dropping to a 5% decline excluding memory.

A precedent exists for a V-shaped recovery for the semiconductor market. At the beginning of the great recession in 2008, the semiconductor market dropped sharply with a 24% quarter-to-quarter decline in 4Q 2008 and a 16% decline in 1Q 2009. The severe economic contraction led electronics manufacturers to cut inventories in preparation for a potential severe drop in demand. As it turned out, electronics markets did not see a major impact from the recession. PC units grew 5% in 2009. Mobile phone units dropped 3% in 2009, but the newly emerging smartphone market was a booming. The semiconductor market had a steep recovery, with 20% quarter-to-quarter growth in 2Q 2009 and 3Q 2009. By 4Q 2009 the market was basically back to pre-recession levels.

Our Semiconductor Intelligence forecast is more of a U-shape than a V-shape. A sharp drop in 2Q 2020 should be followed by a relatively stagnant market in 3Q and 4Q 2020. Growth is expected to pick up in the first half of 2021. We expect the semiconductor market will grow 10% to 15% in 2021.

Also Read:

COVID-19 and Semiconductors

Semiconductor Recovery in 2020?

CES 2020: still no flying cars

May 26, 2020April 26, 2022

Effect of Design on Transistor Density

Effect of Design on Transistor Density
by Scotten Jones on 05-26-2020 at 10:00 am
Categories: Semiconductor Services, TechInsights, TSMC
4 Comments

I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes based on Apple cell phone application processors versus Intel microprocessors, this is not a valid comparison! In this article I will review the metrics I use for transistor density and why I use them and why comparing transistor density on product designs is not valid.

The first comment I want to make is that I am not a circuit designer and therefore I am not familiar with all of the aspects of the decisions that go into creating a design that may impact the transistor density of the final product, but I do have an understanding of the difference in density that can occur across a given process.

Logic designs are made up of standard cells and the size of the standard cells is driven by 4 parameters, metal two pitch (M2P), track height (TH), contacted poly pitch (CPP) and single diffusion break (SDB) versus double diffusion break (DDB).

Cell Height
The height of a standard cell is the metal two pitch (M2P) multiplied by the number of tracks (Track Height or TH). In recent years in order to continue to shrink standard cells the TH has been reduced while simultaneously reducing M2P as part of something called design technology co-optimization (DTCO). One key aspect of reducing TH is that the number of fins per transistor must be reduced at low THs due to space constraints, this is called fin depopulation. If you reduce the number of fins per transistor you get less drive current from each transistor unless you do something else to compensate for it such as increasing fin height, therefore DTCO.

Cell Width
The width of a standard cell depends on contacted poly pitch (CPP), whether the process supports single diffusion break (SDB) or double diffusion break (DDB) and the type of cell. For example, a NAND Gate is 3 CPPs in width with a SDB and 4 CPPs in width with a DDB. On the other hand, a scanned flip flop (SFF) cell might be something like 19 CPPs wide with a SDB and 20 CPPs wide with a DDB (this can vary with SFF designs). As you can see the effect on SDB versus DDB has more affect on a NAND Cell size than on a SFF cell.

Cell Options
When discussing process density, I always compare the minimum cell size, but processes offer multiple options. For example, TSMC’s 7nm 7FF process offers a minimum cell that is a 6-track cell with 2 fins per transistor and a 9-track cell with 3 fins per transistor. The 9-trcak cell offers 1.5x the drive current as the 6-track cell but is also 1.5x the size. This illustrates one of the problems when comparing two product designs to each other as a way of characterizing transistor density, a high performance design would have more 9-track cells and therefore lower transistor density than a design targeted at minimum size or lower power with 6-track cells on the same process. Even the preponderance of NAND cells versus SFF cells would affect the transistor density.

Figure 1 summarize the density difference between 6-track and 9-track cells on the TSMC 7FF process. Please note the MTx/mm² parameter is the million transistor per millimeter squared based on 60% NAND cells and 40% SFF cells.

Figure 1. TSMC 7FF Density Analysis

An interesting observation from figure 1 is that a minimum area SFF cell has over 2x the transistor density of a high-performance NAND cell on the same process. There are also many other types of standard cells with varying transistor densities.

Memory Array
Most system on a chip (SOC) circuits contain significant SRAM memory arrays, in fact it is not unusual for over half the die area to be SRAM array.

The 7FF process offer a high density 6-transistor (6T) SRAM cell that is 0.0270 microns squared in area and that works out it 222 MTx/mm². In theory a lot of memory array area on a design could result in higher transistor density, however, as with a lot of things related to comparing process density it isn’t that simple.

While doing a project for a customer I analyzed 3 TSMC SRAM test chips and embed SRAM arrays in 4 Intel chips and 1 AMD chips. The SRAM arrays were on average 2.93x the size you would expect based on the SRAM cell size for the process and the bit capacity of the array. This is presumably due to interconnect and circuitry to access the memory. If we base transistor density for SRAM on the SRAM cells in the array the density drops to 75.84 MTx/mm² although there are certainly some transistor in the access circuitry that this isn’t counting.

Other Circuits
Certain SOC designs may also include analog, I/O and other elements that have significantly lower transistor density than minimum cells.

Conclusion
The bottom line to all this is that if you could implement the same design, say an ARM core with the same amount of SRAM into different processes you could use actual designs to compare process density, but since that isn’t available then some type of representative metric that can be consistently applied is needed. When I compare processes, I compare transistor density for a minimum size logic cell with a 60% NAND cell/40% SFF cell ratio. This is not a perfect metric but compares processes under the same condition. I also want to mention that for processes that are in production my calculations are based on dimensions measured on the product, typically by TechInsights and are not based on information from the individual companies I am covering. I do use information from the company announcements when estimating future process density.

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May 26, 2020April 14, 2022

Design in the Time of COVID

Design in the Time of COVID
by Bernard Murphy on 05-26-2020 at 6:00 am
Categories: Arteris, IP
1 Comment

There’s a lot of debate about how and when we are going to emerge from the worldwide economic downturn triggered by the pandemic. Everyone agrees we will emerge. This isn’t humanity’s first pandemic, nor will it be our last. But do we come out quickly or slowly? And what does the economy look like on the other side, particularly for the domain we care about – electronic design?

The balance of opinion I have seen comes out on the side of a slow recovery. We’re still at least 18 months away from a vaccine that might allow a return to the heady pre-COVID days. Before we get there, early indications are that no matter how eager politicians may be to restart the economy, consumers are going to be a lot more cautious. If we have more repeats of hotspots and lockdowns, that caution is going to become more embedded in our psyches. Worse yet, many of us are going to have a lot less discretionary income. It’s going to take time to get the people who lost jobs back into the workforce and making at least what they were making in 2019.

This has to have some effect on chip and system design. In some areas a positive effect – anything supporting remote work will benefit, particularly datacenters (just look at Intel’s recent performance). Advances in transportation are less clear. I’d guess for at least a year, maybe more, travel restrictions will still be fairly vigorous and we’ll be much more eager to safely distance than have in-person meetings. Companies will like this, too – lower marketing and sales support overhead. Full autonomy in cars was already looking like a long-term bet; I can’t see these changes speeding up that transition. Smartphones, our portable computers, will still do well as will wireless infrastructure (supporting all this increased traffic). Health wearables, if they actually work, could be promising.

Other stuff – cameras, GoPros, scooters, drones, etc., etc. – not so much. Thank our restricted range, also our restricted bank accounts. There’ll still be some applications, e.g. drones for policing, but consumer volume will drop. Even city, county, state and federal spending will drop. We have to pay off that $2T+ somehow, and that with reduced tax revenues. We consumers will pay for what we absolutely must have – remote connectivity, but not clear we’ll have a lot left over after we’ve paid for that. Some design-start volume has to shrink here, quite likely shifting to new health-centric and other COVID-triggered applications.

Now this is just my view. I could be wrong in details, very likely I am. But it’s difficult to believe that while the rest of the economy collapses around us, everything will still be just peachy in chip design and we can carry on doing everything the way we always have. It seems more likely we’ll have to adapt, quite possibly quickly. No problem, we’re used to that.

In the process we’re going to have to re-examine what are our core strengths and what are our weaknesses. We need staffing in new areas (AI, health, …) and that has to come from existing staffing. Is there some part of the operation adding $2-3M in cost per year and limiting new product introductions because that function can handle only 1-2 designs per year? Is there another way we could do that which might cost less and would allow us to spin 5-10 designs per year?

Kurt Shuler (VP Marketing at Arteris IP) has an answer. He tells me there are still a number of good-sized product companies building and maintaining their own on-chip interconnect IP. Not because those fabrics are provably better NoCs – evals against Arteris tend to prove otherwise – but because the need to control the NoC in-house has become axiomatic, not permitting challenge.

The best way to approach such cases unemotionally is through an ROI analysis, comparing costs, turn-times and risk for the in-house approach versus a 3^rd party solution. Arteris IP developed a spreadsheet analysis which will do those calculations for you. You can plug in your own numbers: Volumes, price per chip, cost per chip, time taken in each phase of development, area overhead, etc. This spreadsheet was developed with a major semiconductor company facing similar problems. Well-grounded in their view of reality, not an IP marketing view.

You might want to check this out. You can download the spreadsheet from HERE.

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May 25, 2020January 27, 2022

CEO Interview: Robert Blake of Achronix

CEO Interview: Robert Blake of Achronix
by Daniel Nenni on 05-25-2020 at 10:00 am
Categories: Achronix, CEO Interviews, eFPGA

Achronix came to SemiWiki in 2017 and we added a chapter on the history of Achronix in our update version of “Fabless: The Transformation of the Semiconductor Industry”. So yes we know quite a bit about Achronix and the FPGA business so it was a pleasure to do a CEO Q&A with Robert Blake. First lets take a look at his biography:

“Robert Blake has worked in the semiconductor industry for over 25 years. Prior to Achronix Semiconductor he was the Chief Executive Officer of Octasic Semiconductor based in Montreal, Canada. Mr. Blake worked at Altera in a variety of sales, marketing and general management roles. As Vice President of Product Planning he was responsible for defining Altera’s programmable logic product solutions. He has been developing ASIC and programmable logic for high speed telecom and network applications for over 17 years. Prior to Altera, he worked at LSI Logic and Fairchild where he developed ASIC technology. He holds a MEng. in Business and Microelectronics and BSc. in Applied Physics & Electronics from the University of Durham in England.”

How is Achronix’s managing through the current business climate? Are you seeing any changes in demand for Achronix FPGA and eFPGA IP?
Achronix continues to accelerate the development of both our 7nm Speedster7t FPGA product family and our Speedcore eFPGA IP. Even with the expected slow down in the global economy this year we will have a record year for sales with strong demand for all of our new products including Speedster 7t FPGAs, Speedcore eFPGA IP and our new VectorPath accelerator cards. We are seeing new design activity for our products in all geographies and target markets including compute acceleration, communications infrastructure, 5G wireless, test and measurement and most recently automotive. I am proud of the seamless transition that our worldwide employees have made to working from home. We have provided all of our employees the resources, connectivity and home office equipment necessary to ensure they can maintain their productivity. We are continuing to hire broadly in sales, design and software engineering, application and marketing. Overall this is the time for Achronix to push firmly on the accelerator peddle to ensure we will exit this global pandemic with a strong product portfolio and expanded global workforce to support new design activity with our products.

What customer requirements will drive further innovation in the FPGA industry?
Customers ask for our help to innovate their products. Our technology can be applied to solve a broad range of data acceleration challenges. At a high level, they need more system performance, but they must deliver this performance at a lower cost and reduced power consumption. Our products blend ASIC level performance and power efficiency with the flexibility inherent in FPGAs, that enables them to quickly adapt to changing workloads and algorithms. These requirements, especially the need to adapt to ever changing data processing requirements, will drive continued innovation in the FPGA industry.

What is Achronix’s strategy to differentiate and compete with Intel and Xilinx?
Unlike some of our competitors, we recognized very early that there are three critical components required to build the best FPGA for data acceleration applications. First, we needed to develop the most flexible logic, embedded memory and advanced compute engines. Next, we needed very high bandwidth external memories (GDDR6) and seamless connectivity to the highest performance PCIe and Ethernet interfaces – Speedster7t includes multiple ports of PCIe Gen 5 and 400G Ethernet. The third, and probably most critical component of our Speedster7t FPGA family, is the addition of a very high performance, low latency 2D NoC. High speed compute and networking applications require computation on vast amounts of data and the Speedster7t 2D NoC is the highest bandwidth and most efficient way to move this data between the communications ports, external memories and the core compute or data processing fabric. The data in these applications is like the fuel flow to a high performance engine. If you starve the engine of fuel you lose performance. We have solved all these problems in our new Speedster7t FPGA family.

Why did Achronix start offering eFPGA IP in addition to standalone FPGA devices?
The strategy to offer eFPGA IP was obvious if you simply look at the trends in the semiconductor industry for the last 50 years. Companies integrate more functionality. They look at components that are on their printed circuit boards and ask three simple questions: are adjacent product compatible from a silicon process standpoint; will they add value if integrated; and will they improve performance, reduce power consumption and reduce board area? Back in the 80’s, most companies used standalone CPUs from Motorola or National Semiconductor. Then ARM came along and offered a large range of CPU cores for integration. Achronix has quickly established ourselves as the leader in delivering high performance eFPGA IP cores. Our customers have integrated custom sized eFPGA IP with exactly the resource mix of logic and memories and compute engines that their application requires. They are already being used in high volume applications with greater than 10M eFPGA IP cores shipped per year.

The primary reason to integrate embedded FPGA fabric is higher performance. Integration eliminates performance and latency bottlenecks between an ASIC and a standalone FPGA, but there are other significant advantages as well including up to 90% reduction in BOM cost and less than 1/2 the power consumption when compared to standalone FPGA solution. Achronix is the only company to offer both high performance standalone FPGA devices and a cost migration path to integrate that same technology into a customer ASIC. We believe this will be a growing trend where unique data acceleration challenges cannot be adequately solved by off-the-shelf FPGA solutions and where Speedcore eFPGA IP is a perfect fit.

What applications are you targeting for your new 7nm Speedster7t FPGA?
Speedster7t FPGAs address a growing need for data acceleration challenges in applications such as networking, data center, test and measurement, compute acceleration, AI/ML, 5G and military applications.

How do you think Achronix’s business will do over the next 3 to 5 years?
Achronix financials are strong and our innovative technology portfolio will enable us to enjoy significant growth over the next 3-5 years. We have tremendous interest from an expanding customer base that will use our latest generation products to deliver new levels of performance innovations in their products. We continue to invest in both our hardware and EDA software tools together with our partners to accelerate the design phase and adoption of our technology. During this challenging time we will continue to innovate and find new ways to effectively deliver our technology into customer’s systems. We are exited about our future.

About Achronix Semiconductor Corporation
Achronix Semiconductor Corporation is a privately held, fabless semiconductor corporation based in Santa Clara, California and offers high-performance FPGA and embedded FPGA (eFPGA) solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, datacenter and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products. The company has sales offices and representatives in the United States, Europe, and China, and has a research and design office in Bangalore, India..

Follow Achronix
Website: www.achronix.com
The Achronix Blog: /blogs/
Twitter: @AchronixInc
LinkedIn: https://www.linkedin.com/company/57668/
Facebook: https://www.facebook.com/achronix/

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May 25, 2020August 25, 2020

China’s Position in the Global Semiconductor Value Chain

China’s Position in the Global Semiconductor Value Chain
by Bart van Hezewijk on 05-25-2020 at 6:00 am
Categories: China
8 Comments

In this third article about China’s role in the global semiconductor industry I analyse the current state of affairs of the Chinese semiconductor industry in different segments. In the previous articles, I looked at the possible effects of a US-China decoupling in the semiconductor industry and the impact of the Big Fund and Chinese investments in semiconductor R&D. Both articles are available in Chinese as well: decoupling, Big Fund (文章翻译成中文: 脱钩, 大基金). In my next article that will be published soon, I will give an updated analysis of the impact of the US-China tech war on the semiconductor industry.

China aims to accelerate the development of the domestic semiconductor industry and reduce the reliance on imports of chips. But the semiconductor industry’s global value chain spans a wide variety of segments such as equipment, materials, software, design, manufacturing, assembly and testing.

One of the conclusions of my previous article was that Chinese (government) investments are often focused on increasing manufacturing capacity and acquiring existing technology instead of real new technology development. Besides having fabs to actually make chips, the tools and equipment needed for chip manufacturing and testing, the software needed to design chips, and the design capabilities themselves are all important in the semiconductor value chain.

In this article I look at the position of (mainland) China, the United States (US), and the rest of the world (ROW) in five different segments of the semiconductor value chain: equipment (EQP), Electronic Design Automation software & Intellectual Property core (EDA & IP), design/fabless & Integrated Device Manufacturer (DES & IDM), foundry (FOU), and Outsourced Semiconductor Assembly & Test (OSAT).

Table 1 shows the combined revenues of the major companies in these five segments for each of the three regions. I included the sales data of 136 companies: 27 equipment (6 from China, 13 from the rest of the world, and 8 from the United States), 9 EDA and IP (1 CN, 4 ROW, 4 US), 76 design and IDM (30 CN, 23 ROW, 23 US), 12 foundry (4 CN, 7 ROW, 1 US), and 12 OSAT (5 CN, 6 ROW, 1 US). Sales data is available from the annual report for listed companies, but unfortunately there are quite some relevant semiconductor companies that are not listed (e.g., Arm, GlobalFoundries, HiSilicon, Kioxia, Mentor Graphics, UNISOC). For 15 of those I based the sales data on publicly available information. For another 65 companies no sales information was available so they are not included in the analysis, which means the consolidated numbers in this article are a lower limit of the actual numbers. I would like to emphasise that the list of companies mentioned in this article is by no means exhaustive, but I believe it provides a representative overview of the global semiconductor value chain (with the materials segment excluded). As the objective of this article is to provide an overview of the Chinese semiconductor industry, I included more (and smaller) companies from China. For the rest of the world and the United States I included only the largest and most important companies. (i)

Table 1: Semiconductor sales by segment and region.

If we look at all sales data across five segments the whole semiconductor industry combined sales is US$ 571.8 billion. US headquartered companies account for 47%, companies from the rest of the world for 45%, and China based companies for 7%. For all three regions, design & IDM is the segment with highest sales. Globally, design & IDM accounts for 71% of all sales, followed by equipment (13%) and foundry (10%). OSAT (5%) and EDA and IP (2%) generate considerably less revenue.

China is relatively strong in OSAT, mainly because of JCET which accounts for 57% of China’s revenue in this segment. For EDA & IP and especially equipment, China is far behind the United States and rest of the world. The rest of the world region’s strongest segment is foundry, because of TSMC (78% of the region’s foundry revenue) and UMC (11%) from Taiwan. In addition, the rest of the world region is leading in OSAT, again because of Taiwanese companies such as ASE (73% of the region’s OSAT revenue) and PowerTech (12%). The US’ main strengths are in design & IDM and EDA & IP. Intel is the world’s largest semiconductor company based on revenue (US$ 72 billion) and Micron, Qualcomm and Broadcom all have more than US$ 20 billion sales. For EDA software all three global leaders are US headquartered: Synopsys, Cadence Design Systems, and Mentor Graphics (owned by German Siemens). Equipment is a narrow victory by the rest of the world region, led by Dutch ASML (#2 equipment company globally) and Japanese Tokyo Electron (#3), over the US, with Applied Materials (#1), Lam Research (#4), and KLA (#5).

Figure 1 also represents the sales data and includes all companies that account for at least 10% of sales of their segment in their own region.

Figure 1: Semiconductor sales by segment and region.

Further breaking down the revenues for rest of the world gives the following ranking (sales above US$ 10 billion):

United States, US$ 270.9 billion
Korea, US$ 80.9 billion
Taiwan, US$ 75.9 billion
Japan, US$ 50.0 billion
China, US$ 41.3 billion
The Netherlands, US$ 25.4 billion

Korea is home to two of the largest IDMs, Samsung (#2, US$ 56 billion sales) and SK Hynix (#3, US$ 23 billion). In addition to the foundry and OSAT companies mentioned above, Taiwan is also home to design companies such as MediaTek, Novatek and Realtek. Japan’s strength is in equipment with Tokyo Electron, Dainippon Screen and Advantest, and IDM with Kioxia, Sony Semiconductors Solutions, and Renesas, amongst others. China’s largest semiconductor companies are design companies Unis and HiSilicon, foundry SMIC and packaging and test provider JCET. More than half of the Netherlands’ semiconductor revenue is generated by lithography equipment supplier ASML but ASM International (equipment, US$ 1.4 billion), NXP (IDM, US$ 8.9 billion) and Nexperia (IDM, US$ 1.4 billion) also contribute generously.

In the remainder of this article I will look at the five segments separately, with special attention for the performance of Chinese companies compared to the global leaders.

Equipment

Many different types of tools and equipment are needed to make chips. Important steps in the IC manufacturing process include lithography, ion implantation, deposition (e.g., CVD, PVD), etching, cleaning, and testing. The major equipment suppliers are from the US, Japan and the Netherlands, but China is also trying to develop its domestic semiconductor equipment industry.

The lithography equipment segment is dominated by Dutch ASML with a market share of 85% and the only relevant competitors are Canon and Nikon from Japan. China’s sole lithography equipment maker is Shanghai Micro Electronics Equipment (SMEE) and its most advanced tool at present enables 90nm chip production. ASML sold their first lithography systems that could produce complex 90nm chips in 2004 already (16 years ago!).

For the deposition equipment segment there are more competitors. Some of the big players are active in PVD and CVD such as Applied Materials (US), Tokyo Electron (JP) and Lam Research (JP), but also smaller companies such as Aixtron (DE), ASM International (NL), Evatec (CH) and Ulvac (JP). NAURA, resulting from the 2017 merger between Sevenstar Electronics (established in 2001) and Beijing North Microelectronics (NMC, also 2001), is the largest semiconductor equipment company in China and active in this field.

Another more established Chinese equipment company is Advanced Micro-fabrication Equipment (AMEC). The Shanghai-based company that produces etch equipment and MOCVD tools was founded in 2004 and was in the first batch of companies to get listed on the new Shanghai Stock Exchange Science & Technology Innovation Board (or STAR Market) in 2019. Qualcomm participated in AMEC’s B round in 2007 and is still one of its shareholders. AMEC’s etch equipment is verified by TSMC for its 7nm process.

Other companies active in cleaning, packaging and testing equipment include Advantest (JP), ASM Pacific Technology (SG), Dainippon Screen (JP), and Teradyne (US). More Chinese semiconductor equipment companies worth mentioning are Hangzhou Changchuan Technology, Kingsemi, and PNC Process Systems but their revenues are well below US$ 150 million.

Table 2: Semiconductor equipment companies’ sales and R&D spending per region.

EDA & IP

Electronic Design Automation software and IP core is another area where China still lags far behind. The vast majority of the Chinese EDA market is taken by the three global leaders Synopsys, Cadence, and Mentor. There are some Chinese companies active in the EDA segment though, such as Cellix, Empyrean, ProPlus, Semitronix, and Xpeedic. Empyrean seems to lead the Chinese domestic field, but I could not find financial information for any of these companies. Cellix is reported to be preparing for a listing on the STAR market and ProPlus closed an investment round in April 2020 in which Intel reported it participated.

Table 3: EDA software & IP core companies’ sales and R&D spending per region.

An IP core is intellectual property of a licensing party that can be used as a building block for chip design. IC design companies use third party IP and their own IP to design their chips. The leading company in this field is UK-based but Japanese (Softbank) owned Arm Holdings. Basically, all smartphones and most IoT devices use Arm’s processor architecture. Softbank closed the Arm acquisition in September 2016, and just 1.5 years later, in April 2018, Arm China (also known as Arm mini China) was created. Arm China is 51% controlled by a consortium of Chinese investors and Arm owns 49%. Arm China sells and licenses Arm (UK) technology in China but has also gradually moved to developing its own (Chinese) IP. For example, Arm China has developed a design that allows Chinese-made chips to run a cryptographic algorithm built by China’s State Cryptography Administration.

Imagination Technologies is also UK-headquartered but was acquired by Cayman-based and Chinese funded private equity fund Canyon Bridge in November 2017. In April 2020 Imagination announced plans to appoint new board directors from China Reform Holdings, the major investor in Canyon Bridge. After the UK government expressed concerns this proposal was withdrawn. Imagination mainly develops IP for Graphic Processor Units (GPUs). Apple used to be Imagination’s biggest customer until 2016 and earlier this year they signed a new multi-year license agreement under which Apple will have access to a wider range of Imagination’s IP.

Previously mentioned Synopsys and Cadence are also active in the IP core licensing field, and so is US-based Rambus, mainly licensing memory technology. In China, VeriSilicon is the leading (but loss making) company in this field. Established in 2001, it’s investors include Intel, Samsung, Xiaomi, the Big Fund, and Walden International. VeriSilicon has announced the intention to list on Shanghai’s STAR market.

Besides the Arm architecture, there are only a few other processor architectures. Like Arm, MIPS and RISC-V are so called RISC (Reduced Instruction-Set Computer) architectures and x86 is a CISC (Complex Instruction-Set Computer) architecture. In general, CISC is more suitable for high performance processors (complexity and speed; e.g., servers) and RISC for power efficiency (e.g., smartphones).

MIPS Technologies developed the MIPS architecture in the 1980s and licensed it to chip designers. Imagination Technologies bought MIPS Technologies in 2013 and sold it to US based Wave Computing prior to the Canyon Bridge acquisition of Imagination in 2017. Wave Computing filed for bankruptcy in April 2020 but there are reports that MIPS will continue its business independently. MIPS is not nearly as successful as Arm but in China it is used by Loongson (formerly known as Godson and creator of China’s first domestic CPU) and Ingenic (designing CPUs and IoT and wearables chips).

RISC-V is an open source project that started at UC Berkeley in the US in 2010 and aims to provide royalty free instruction set architectures. RISC-V started in academia but in 2015 the RISC-V Foundation was established to create a community for standardisation and improvement through open collaboration. In March 2020 the RISC-V International Association (RVI) was incorporated in Switzerland after reflecting on the geo-political landscape and to calm “concerns of political disruption to the open collaboration model”. RVI mentions explicitly on its website that “there have not been any export restrictions on RISC-V in the US and we have complied with all US laws. The move does not circumvent any existing restrictions, but rather alleviates uncertainty going forward.” RVI has never received or pursued funding from any government and currently has more than 500 members, including Alibaba, Huawei, the Institute of Computing Technology of the Chinese Academy of Sciences, and VeriSilicon from China. US members include Western Digital, Nvidia, and Rambus. RISC-V is relatively new so no major competition for Arm yet, but the community is moving fast and in the current geopolitical climate open source, which is not export-controlled by definition, may be the way forward for Chinese chip design companies.

Design & IDM

For this article I combined the fabless design companies and Integrated Device Manufacturers in one segment as they all have the capabilities to design chips. The fabless design companies rely on foundries to manufacture the chips they designed, while IDMs make their chips in-house. Design & IDM is the largest segment of the semiconductor value chain across regions (72% of total semiconductor sales for China, 61% for rest of the world, and 81% for US); it also has the most companies included in this analysis for each region. The world’s biggest semiconductor companies are all active in this segment: IDMs Intel, Samsung, SK Hynix, and Micron, and fabless design companies Qualcomm and Broadcom. They all have more than US$ 20 billion sales; only foundry TSMC belongs to the same category with US$ 34.6 billion sales. Within the Design & IDM segment, the US is the clear leader with 54% of its sales, followed by the rest of the world with 39% and China’s 7%.

Table 4: IC design companies’ and IDMs’ sales and R&D spending per region.

The biggest Chinese chip design companies are Unis (also known as Unisplendour) an HiSilicon (fully owned by Huawei). HiSilicon develops SoCs (System on a Chip; multiple components such as CPU, GPU, and memory on one chip) based on Arm architecture. HiSilicon designs smartphone chips (Kirin), server chips (Kunpeng), and smartphone modems (Balong). The newest Kirin 810 outperformed competitor Qualcomm’s Snapdragon 855 SoC in the AI Benchmark test. Qualcomm is the global market leader in smartphone SoCs and has held the same position for the China market for a long time. Until Q1 2020 when HiSilicon led the China smartphone SoC shipments ranking for the first time. COVID-19 has a big impact though, as smartphone SoC shipments decreased more than 44% compared to Q1 2019.

Unis is part of the Tsinghua Unigroup ecosystem. Unigroup’s subsidiaries include fabless companies Pango Microsystems, Tongxin Microelectronics, Unic Memory, Unigroup Guoxin, UNISOC (formerly known as Spreadtrum), and Unis; foundries UniIC Semiconductors, XMC and YMTC; and OSAT company Unimos. Unis and Guoxin are listed companies. UNISOC primarily designs entry-level smartphone and feature phone chips, which are very popular in India and Africa.

Another Chinese State-Owned Enterprise (SOE) that is very active in the semiconductor industry is China Electronics Corporation (CEC). CEC’s companies include fabless Anlogic, CE Huada Tech, Huada Semiconductor, Microne, Phytium Technology, Shanghai Belling, Solantro (a Canadian company acquired in 2018 and now known as Huada Semiconductor North American R&D Centre), and Solomon Systech; foundry GTA Semiconductor; and OSAT company Chipadavanced. CE Huada Tech, Shanghai Belling, and Solomon Systech are listed companies.

Chinese consumer electronics company (and smartphone vendor) Xiaomi has been active in chip design with its subsidiary Pinecone established in 2014. Early 2017 Pinecone revealed the Surge S1 chipset, but Xiaomi’s 5C smartphone which used the S1 failed because of high power consumption and heat output. In April 2019 Xiaomi announced it would spin off and take a 25% stake in a new company Big Fish Semiconductors to focus on the development of AI and IoT chips. Pinecone (51% owned by Xiaomi and 49% by China’s Datang Telecom) will keep developing smartphone chips. Xiaomi also invested in IP provider VeriSilicon and is its second biggest shareholder behind the Big Fund.

The Chinese design companies mentioned above mainly use Arm architecture but some Chinese companies work with x86 architecture. Because x86 is a CISC architecture, it is the dominant architecture in the server market. Recently though, Arm and RISC-V based processors seem to get some more traction. Intel is market leader in the x86 processor market but AMD (also from the US) has been gaining market share over the last years thanks to its Ryzen chip architecture. Besides them, only VIA Technologies from Taiwan has a x86 CPU license but VIA has not been successful at making the products to get closer to Intel and AMD’s market share.

Interestingly though, on May 8 the first Chinese PCs with domestically developed x86 CPUs were released. They use the KX6000 processor series made by Zhaoxin, a joint venture between VIA Technologies and the Shanghai local government established in 2013. The performance of these KX6000 processors, which are based on architecture developed by VIA’s US subsidiary Centaur Technology, is still far behind Intel and AMD’s current offerings, but it’s definitely suitable for its intended government use. This is an important step in China’s plans to reduce dependence on foreign technology and Zhaoxin has ambitious plans to bridge the gap with Intel and AMD.

AMD also set up a joint venture in China, with partners including high performance computing maker Sugon and the Chinese Academy of Sciences. Tianjin Haiguang Advanced Technology Investment Co (THATIC or Higon), set up in 2016, actually comprises two JVs with AMD holding 51% shares of Chengdu Haiguang Microelectronics Technology (also known as HMC) and 30% of Chengdu Haiguang IC (also known as Hygon). AMD exported IP to subsidiary HMC and Hygon would customise the designs before they were sent to GlobalFoundries in the US for manufacturing. This allowed the Chinese side to call the processors ‘Chinese’ and AMD to comply with all relevant export control legislation. Until June 2019 that is, because then the US government added AMD’s JVs to the Entity List because Sugon had acknowledged military end uses and end users of its high-performance computers. The consequence is that US companies need to apply for a license before exporting products and technology to these entities and the US government follows a ‘presumption of denial’ policy.

Intel set up a collaboration with Tsinghua University and Montage Technology in 2016. Based on Intel’s x86 Xeon architecture and Tsinghua developed technology, Montage designed the Jintide CPU. Montage Technologies is listed on Shanghai’s STAR market since July 2019 and Intel owns 9% of its shares.

One Sino-American collaboration in the semiconductor industry that did not last long is the joint venture Qualcomm set up in 2016 with the Guizhou provincial government. The JV, Huaxintong Semiconductor Technologies (HXT), 55% owned by Guizhou province and 45% owned by Qualcomm, focused on designing server chips based on Arm architecture. In November 2018 HXT announced that the StarDragon 4800 had started mass production. This processor is similar to Qualcomm’s Centriq 2400 series with a modified crypto module to meet China’s commercial cryptographic algorithms standards. In April 2019 it was reported that the joint venture would shut down.

RISC-V architecture is another area where Chinese companies have become increasingly active. Alibaba Group acquired Hangzhou C-Sky Microsystems in 2018 and reorganised its chip R&D activities into Pingtouge Semiconductor (also known as T-Head). In July 2019 Pingtouge announced it developed a 16-core Xuan Tie 910 RISC-V CPU (XT910) and claimed it was the most powerful design based on RISC-V IP yet. Two months later Alibaba also announced the Hanguang 800 AI inference chip made with TSMC’s 12nm process. The Neural Processing Unit (NPU) is capable of handling complex tasks such as product search, image analysis, and personalised recommendations on Alibaba’s e-commerce platforms.

Foundry

The semiconductor pure play foundry segment is dominated by the rest of the world region, mainly because of Taiwan’s TSMC, the world leader in this field by far. The number two (UMC) and three (Vanguard) foundries from the rest of the world region are also based in Taiwan. The only US-based foundry is Abu-Dhabi owned GlobalFoundries and in China the largest foundries are SMIC and Huahong Grace. For some other Chinese foundries such as Huali (also from Huahong Group), YMTC and XMC (both part of Tsinghua Unigroup), and CXMT, I have not found financial data.

Table 5: Foundry sales and R&D spending per region.

SMIC has made quite some progress over the years and is now capable of 14nm mass production, although the defect rates are still very high according to some sources. Industry leader TSMC and IDM Samsung are already mass producing 7nm (and TSMC starting 5nm), while GlobalFoundries announced it stopped 7nm development because of the high costs involved. On May 11 it was announced that SMIC had started mass production of Huawei/HiSilicon’s Kirin 710A on its FinFET 14nm process. Although these chips are not current state-of-the-art (Kirin 710 was launched in July 2018), this is a significant development for China’s semiconductor industry as it is the first time that Huawei uses a foundry other than TSMC to make its smartphone chips.

Other Chinese foundries, focused on developing memory chips, are YMTC and CXMT. The memory market is dominated by Samsung and SK Hynix from Korea and US-based Micron. On April 13, YMTC announced it has developed 128-layer 3D NAND flash memory chip X2-6070, based on its own Xtacking architecture. Whether X2-6070 will indeed be a success depends on multiple factors, including the timing of mass production (probably H1 2021) and yield (the proportion of chips on a wafer that work properly). So after designing the memory chip, getting the production process right will be the next big challenge for YMTC.

CXMT, China’s new DRAM memory maker (established in 2016, then known as Innotron), announced at the end of April that they signed a long-term patent license agreement with US-based Rambus to get access to a wide variety of DRAM patents. This deal will strengthen and diversify CXMT’s IP portfolio. Through previously signed licensing agreements, CXMT already has access to Qimonda’s IP (Qimonda spun off from Infineon in 2006 and was the world’s second largest DRAM company at the time but ceased operations in 2011).

OSAT

Half of the top 10 global Outsourced Semiconductor Assembly and Test (OSAT) companies are from Taiwan. Market leader ASE Group’s market share is 47%, followed by Amkor from the US and JCET from China. With the other 4 Taiwanese companies, two Chinese companies (TFME and Tianshui Huatian) and one Singaporean company complete the top 10.

Table 6: OSAT companies’ sales and R&D spending per region.

This analysis shows that China is still a relatively small player in the global semiconductor value chain, except for the OSAT segment where China holds more than 20% of the global market. There are 3 Chinese companies in the global top 6 OSAT companies, while 6 years ago only JCET made the top 10. This also shows that the developments in the Chinese semiconductor industry can go fast.

However, in other segments, particularly semiconductor equipment and EDA & IP, China is still far behind. Although AMEC has developed tools which are used in many foundries, AMEC is still a small player (around #20) among all the semiconductor equipment makers ranked by revenue. And size matters. To stay competitive in the semiconductor industry, companies need to invest in R&D and with higher sales companies can invest more in new technological developments and innovation.

Table 7: Average R&D investment as percentage of sales across segments and regions.

There are no huge differences between the three regions when it comes to companies’ average R&D spending as percentage of sales. American design & IDM companies spend more on R&D than their competitors from China and the rest of the world, and Chinese foundry and OSAT companies on average spend a larger part of their revenue on R&D than others. For the foundry segment, this is mostly attributable to SMIC’s R&D spending (22.1%) which is much higher than any other foundry in the world (Chinese Silan ranks second with 10.7% and TSMC is third with 8.5%). Looking at the actual R&D expenditures (in dollars), China’s share of global R&D expenditures is indeed higher than its share of global sales for the foundry (18% vs 8%) and OSAT (23% vs 21%) segments. However, for both these segments the rest of the world’s R&D expenditures are much higher than those of China; for foundry the rest of the world region spends 4.6 times as much on R&D as China, and for OSAT they spend 2.9 times as much.

For the equipment and EDA & IP segments there are no apparent differences between regions (and like for foundry and OSAT, the sample sizes on which these averages are based are small) but for design & IDM, US companies on average spend a higher percentage of their revenue on R&D than others. Because these are also the biggest companies in the whole industry, measured by sales, this is a major competitive advantage of the American semiconductor industry. Although US design & IDM companies account for 54% of global design & IDM sales, they are responsible for 72% (or a combined US$ 38.9 billion for the 22 companies included in this analysis) of global R&D expenditures in this segment. The amount of money Intel spends on R&D, US$ 13.4 billion, is higher than the annual revenue of all semiconductor companies in the world except 8 (Samsung, TSMC, Qualcomm, Micron, SK Hynix, Broadcom, Applied Materials, and Texas Instruments).

The absence of major differences in R&D spending as percentage of sales between regions for the equipment and EDA & IP segments does not mean that it will be easier for China to catch up in these areas. For example, ASML spends around US$ 2.2 billion on R&D, which is twice the annual revenue of all six Chinese semiconductor equipment companies included in this analysis combined. For EDA the whole industry basically depends on the three major vendors Synopsys, Cadence, and Mentor. Although quite a few Chinese companies are developing EDA tools, none of them are competitive as they are not comprehensive enough (no complete design flow) and because the most advanced fabs and foundries will not use them, it is extremely difficult for them to get a better understanding of the processes and improve their software.

Fortunately for China, some developments provide a more positive outlook for growing the domestic semiconductor industry. The establishment of Arm China, the acquisition of Imagination Technologies, Intel investing in Montage Technology and ProPlus, the IP licensing deal between Rambus and CXMT, and the whole development of the RISC-V movement, could bring opportunities to strengthen China’s semiconductor industry. In the chip design field, HiSilicon is already world class and entered the top 10 of semiconductor sales leaders for the first time in Q1 2020 according to IC Insights. Recent achievements including Zhaoxin’s first domestically developed x86 CPU, Pingtouge’s RISC-V based CPU and AI inference chip, and YMTC’s 3D NAND flash memory chip, indicate progress is certainly being made in Chinese chip design. The recent announcement that SMIC is mass producing HiSilicon’s Kirin 710A on 14nm FinFET is a significant development for China’s chip manufacturing.

But… the challenges for particularly the equipment and EDA segments remain, and it is extremely difficult to catch up with industry leaders (also in design and manufacturing) when they spend much more on R&D and thus maintain their technology leadership. The establishment of the Big Fund is one (small) step to help Chinese semiconductor companies to overcome this gap, and recently there seems to be a trend for more Chinese semiconductor companies to go public, for example on Shanghai’s STAR market. AMEC and Montage Technology are already listed there, SMIC, VeriSilicon and Cellix announced plans to do so, and Imagination Technologies, UNISOC, and Horizon Robotics are also rumoured to file for an IPO. Although companies understandably look for more funding and resources, they should also keep in mind that the interests of investors (quick returns) do not always align with those of the companies themselves (long term commitment to R&D). There are no quick wins for companies that still need to establish their position in the global semiconductor value chain.

And then of course the biggest stumbling block for the development of China’s domestic semiconductor industry is the current geopolitical climate and recent actions taken by the US government that restrict American, and since May 15, 2020 also non-American, companies from doing business with some Chinese semiconductor companies. I will write more about the impact of the US-China tech war on the semiconductor industry in my next article. So stay tuned!

I would like to end this article with a suggestion for further reading that really gave me a better understanding of the history and development of the Chinese semiconductor industry. It is very informative and I really enjoyed reading the article originally written by Boss Dai (戴老板), published on his WeChat account on May 15, 2018: 中国芯酸往事. The article is translated into English by Jeffrey Ding and Lorand Laskai and published in the July 8, 2019 ChinaAI newsletter: The Sour Past of “China Chips”.

Bart van Hezewijk
Officer for Innovation, Technology & Science
Netherlands Innovation Network
Consulate-General of the Kingdom of the Netherlands in Shanghai
@bartvanhezewijk

(i) Note on data collection

For this analysis of the global semiconductor value chain I identified 201 companies: 100 from China, 59 from rest of the world, and 42 from the US. 121 of these companies are listed so I could get their sales and R&D spending data from their annual reports. The annual report used is the report for the fiscal year ending 31 December 2019 or earlier that year, except for Aixtron, Goodix, JCET, PowerChip, Tower Semiconductor (31 Dec ‘18), Ambarella (31 Jan ‘20), and Marvell (1 Feb ‘20).

For another 15 companies I used other publicly available data:

Arm (Softbank Group Annual Report 2019), Cambricon, GlobalFoundries, Imagination Technologies, Kioxia, Nexperia, Vanguard International Semiconductor (VIS Consolidated Financial Statements), and VeriSilicon.
For GalaxyCore, HiSilicon, Huada Semiconductor, Integrated Silicon Solutions Inc, Sanechips Technology, and UNISOC: Trendforce (2018 revenue).
For Mentor Graphics I calculated the 2019 revenue relative to Synopsys’ and Cadence’ 2019 revenue, based on their share of their combined revenues (Synopsys 46%, Cadence 33% and Mentor 21%) in 2016 and 2017 (latest available annual reports of Mentor).

For some companies their semiconductor business is a part of their total business. For these companies I only included the semiconductor revenue:

Fujitsu Semiconductor: LSI Devices within Device Solutions, 5.3% of Fujitsu Group total revenue.
Hitachi Hitech: Electronic Device Systems, 20.1% of total revenue.
IBM: Systems (includes Servers & Storage Systems), 9.9% of total revenue.
Jusun Engineering: Semiconductor (Display and Solar Cell not included), 52% of total revenue.
Mitsubishi Electric: Electronic Devices, 4.4% of total revenue.
Samsung: Semiconductor within Device Solutions (inter-company revenue not included), 28% of Samsung Electronics total revenue.
Tianjin Zhonguan: Semiconductor Device (Semiconductor Materials and New Energy not included), 0.83% of total revenue.
Wonik IPS: Semiconductor (Display and Solar not included), 55% of total revenue.

Some large companies that are active in the global semiconductor value chain are left out from the data analysis because they do not report financial data for their semiconductor related business or their data was not specific enough to be included in this analysis, e.g., Apple (US, DES), Baidu (CN, DES), Bosch (DE, DES), Canon (JP, EQP), and Nikon (JP, EQP).

May 24, 2020January 11, 2022

Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am
Categories: Lithography

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation. Probably the most well-known scaling limiter for transistors is the short-channel effect (SCE) which has been covered for many years and updated for recent transistor developments like FinFETs. Much less well-known but still very important and persistent is contact resistance, i.e., the electrical resistance of the narrow contact to the much larger transistor. A higher contact resistance is damaging in either of two ways: (1) less current at the same operating voltage, which reduces performance, or (2) higher voltage for the same driving current, which increases power consumption.

The contact resistance (Rc) is usually characterized by the “contact resistivity” which actually has the units of resistance x area (ohms-cm^2). The actual resistance is computed from contact resistivity by dividing contact resistivity by the contact area. In Figure 1, the trend of contact resistance is plotted from three different references, published over a period of ten years.

Figure 1. Contact resistance trends, from various studies from 2008 to 2018 [1-3].

The earliest reference [1] is from 2008, published by Stanford. It was based on projections from the 2005 ITRS roadmap projection at the time. The second reference is from 2013 [2], from an interesting paper discussing the use of an interfacial layer. Half the authors listed were affiliated with Applied Materials, so the data for it on the graph is labeled as “AMAT”. The contact resistivity used here was 3.5e-8 ohm-cm^2. The third, most recent reference is from IMEC[3], which presented an atomistic simulation study. Its values are lower than previous projections. Specific assumptions for this case were: n+ doping of 3e20/cm^3, amorphous titanium silicide interface. The resulting calculated resistivity was 4e-9 ohm-cm^2. A lower doping would raise the resistance significantly (Figure 2). For 1e20/cm^3, with over 2 kOhm resistance, even 65 nm size contacts are a problem for many applications.

Figure 2. The contact resistance can be increased significantly by a reduction of doping (from 3e20/cm^3 to 1e20/cm^3 in this case) [3].

The red arrow in the graph marks where we are today at the bleeding edge. At this point, the contact resistance is already over 1.5 kOhm, and this is about 3 times what it was for the 90 nm node. Contact resistivity needs to get to below 1e-9 ohm-cm^2 to avoid becoming prohibitive at ~10 nm scale. Based on IMEC’s results [3], this may require doping over 1e21/cm^3, which is 2% concentration impact in silicon! It would not be the original pure silicon anymore!

Not surprisingly, the move from planar transistors to FinFETs simultaneously changed the way contacts are landed. They don’t land flat on the silicon surface anymore. Instead the contact lands on and wraps around the angled surfaces of epitaxially grown SiGe, which effectively increases the contact area. In a way, transistor contact scaling in 2D already hit the wall, and we are already operating in 3D.

Notation clarification: The notation “1e20” is the same as 1 x 10^20. Likewise, “3e-8” means 3 x 10^-8.

References

[1] L. Wei, J. Deng, L-W. Chang, K. Kim, C-T. Chuang, H.-S. P. Wong, “Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap,” IEEE Trans. Elec. Dev. 56, 312 (2009).

[2] S. Gupta, P. P. Manik, R. K. Mishra, A. Nainani, M. C. Abraham, S. Lodha, “Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts,” J. Appl. Phys. 113, 234505 (2013).

[3] A. Dabral, G. Pourtois, K. Sankaran, W. Magnus, H. Yu, A. de Jamblinne de Meux, A. K. A. Lu, S. Clima, K. Stokbro, M. Schaekers, N. Collaert, N. Horiguchi, M. Houssa, “Study of the Intrinsic Limitations of the Contact Resistance of Metal/Semiconductor Interfaces through Atomistic Simulations,” ECS J. Solid State. Sci. and Tech. 7, N73 (2018).