Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these models work just fine for most purposes. The one important application where modeling the BJT is important is for electrostatic discharge (ESD) protection circuits. ESD can be a serious threat to product yield and reliability. It is important to model ESD events before chips are fabricated to avoid problems during manufacturing and in the field. ESD events involve higher voltages and currents, that can lead to impact ionization as potential builds up across depleted junctions.
Impact ionization can cause avalanche breakdown effects, where large numbers of electrons are broken loose in an accelerating cycle. The movement of carriers during avalanche breakdown creates a current in the substrate that will trigger the BJT. Under these conditions the device is carrying additional current, creating a positive feedback loop that lowers the voltage across the device while increasing current. This is known as snapback, which wreaks havoc on traditional MOS device models.
After snapback the I-V curve shows an increase in current as voltage is increased, up to the point where there is a second avalanche that leads to thermal breakdown of the device. To properly model a Mosfet when used for an ESD application, the above behaviors must be handled by the model. Empirical data for ESD device performance can be obtained through transmission line pulse (TLP) measurements. The resulting table model is called a TLP model. This can be a useful source of information in creating an accurate SPICE model for an ESD device.
In work done at Brazil based RFID chip maker CEITEC, a macromodel was used to comprehensively model these types of devices. They worked together with MunEDA, who develops analog circuit optimization tools, to simulate and adjust the parameters in the device macromodel so that simulated results matched the measured TLP data. The work is summarized in a presentation titled “Parametric Analysis and Optimization of MOSFET Macromodels for ESD Circuit Simulation” by Robert Dettenborn. The resulting macromodel itself is made up of only standard SPICE elements.
Key steps and tools adopted in the approach
The target process was 180nm CMOS. The first step was to establish a proposed topology for a GGNMOS protection device, which in their case contained a standard Mosfet, a parameterized BJT model and resistors for Rsub and Rgate. For the BJT, a MEXTRAM compact model was used because it is suitable for high current and high voltage operation. It is worth noting that the foundry’s BJT model usually cannot be used because the parasitic device is different than a regular BJT. The presentation goes into the specific differences.
The MULT parameter of MEXTRAM compact model was used to adjust the I-V characteristics so they approximated the measured device. This was done with Cadence ADE and Spectre. The final MULT value used was 70. Further tuning was done to determine the initial value of Rsub. Interestingly, after running parametric analysis, the decision was made to remove Rsub, because the avalanche current values matched better without it. The base resistance model of MEXTRAM was then the sole responsible for the substrate resistance behavior of the macromodel. A drain side resistor, Rd, was added, after which further parametric analysis showed that a good value was around 2 Ohms.
The heavy lifting then started with the optimization of the Mosfet macromodel, including the BSIM4 and MEXTRAM models for the active devices. The MunEDA WiCkeD Constraint Editor was used to implement the initial constraints. MunEDA WiCkeD Sensitivity Analysis was used along with Spectre to determine the influence of each of the initial constraint settings. This was done to ensure that the correct upper and lower limits of the parameters were used in the optimization phase.
MunEDA’s Global Nominal Optimization (GNO) and Deterministic Nominal Optimization (DNO) tools were used to optimize the parameters to fit to the TLP curve. Targets performances were set for Vt1, It1, Vh, Ih, and Vt2, which covers the initial triggering point I-V, the holding point I-V, and the breakdown voltage. In addition, an acceptable upper and lower bound for each performance was specified. GNO also uses several settings to control the algorithm. The number of generations was set to 5, the number of samples for each was set to 10,000 and the sample area for the parameters was set to be equal to the upper and lower limits of variation.
In this case acceptable values were reached after the 5 generations of GNO. If GNO did not yield desirable results, further optimization could be performed with DNO. In this case, MunEDA WiCkeD Sensitivity Analysis along with a Sweep Analysis can be used prior, to ensure that the initial parameter values and optimization boundaries are able to produce target performance results without discontinuities. Once this is done DNO can be run and better optimization results can be achieved.
The paper shows that the final results of this flow give a model that fits the TLP data very well. This opens the door to running traditional SPICE simulations to closely examine ESD protection performance and behavior. This is important because characteristics of the ESD device, such as load capacitance, may adversely affect IO performance. With a SPICE macromodel for the ESD device, simulation tests can be run to verify that the protected devices are not exposed to conditions that can lead to failure or degraded performance.
Simulation vs. TLP results for a GGNMOS protection device
It is only possible to summarize the process here, much more detail is contained in the presentation available on the MunEDA website. MunEDA analog tools can be applied to a wide variety of design problems. This is just one example of their utility and usefulness.Share this post via: