IBM and Leti each presented several papers at IEDM including a joint nanosheet paper. I had the opportunity to sit down with Huiming Bu, director of advanced logic & memory tech and Veeraraghavan Basker, senior engineer from IBM and then in a separate interview Francois Andrieu, head of advanced CMOS laboratory and Shay Reboh, Process & integration engineer, of Leti to discuss their work.
IBM has a development line in in Albany at the CNSE center where they developed the 5nm technology they have now transferred to Samsung and they are now doing 3/2nm work. Tool reuse versus 5nm is high although there is a change in device architecture that requires some unique tools. When they start work on a new device, they use test structures to evaluate the device and materials before doing a shrink. If you use node-1 to develop materials and devices, then the shrink becomes an engineering problem.
One IBM paper was “Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications”. One key challenge for horizontal stacked nanosheets is how to achieve multiple threshold voltages (Vts). With FinFETs the current approach is to use stacks of various work function metals but in horizontal nanosheets the sheet to sheet spacing needs to be as small as possible to minimize capacitance and maximize performance.
IBM has a long history of using dipoles to tune Vts. When high-k metal gates (HKMG) were first introduced IBM, used a gate-first approach including the use of dipoles. The rest of the industry went with gate-last and that has become the dominant HKMG approach, but IBM’s early experience with dipoles provide them with experience that is proving useful for nanowires. Replacing a stack of work function metals with dipoles enables multiple Vts in nanosheets and removes a key roadblock to nanosheet adoption.
Another challenge for horizontal stacked nanosheets is the need to first recess the SiGe layers without etching silicon and later to etch out the SiGe layers to release the Si layers, once again without etching silicon. In “A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices” IBM discussed work they have done with Tokyo Electron to use a gas phase isotropic etch (authors note, I believe this is TEL’s Certas Wing tool). They were able to achieve 150:1 selectivity for SiGe(25%) versus Si.
In a third paper we discussed, “Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications” IBM disclosed a process whereby they create a dielectric under the stacked horizontal nanosheet stack reducing parasitic capacitance and improving performance. The dielectric is silicon nitride based but they wouldn’t disclose how it was formed. The initial nanosheet stack is grown right on silicon to provide crystalline epitaxial growth so somehow, they are etching out underneath the stack and refilling.
They also discussed that at a high level nanosheet offer >25% performance improvement at constant power or a 50% power reduction at the same performance versus a 7nm FinFET. 6, 5, 4nm FinFETs will not be as good as a nanosheet. Nanosheets also offer the ability to lithographically define the width creating nanowires for the best electrostatic and nanosheets for higher drive current on the same process. Around 2012 IBM created the name nanosheet and in 2015 with GLOBALFOUNDRIES and Samsung published a 5nm nanosheet paper. Authors note, Samsung has announced a 3nm nanosheet process due in 2021 based on the joint work.
First generation nanosheets will be silicon. I asked about alternate materials for future nanosheets and they said unless there is a breakthrough in the back-end-of-line (BEOL) or parasitics, alternate materials won’t be worth the complexity. You can align the silicon orientation for nanosheets for higher mobility. Going beyond nanosheets to CFETs (basically stacked nanosheets where n and p type devices are stacked) you can orient nFETs to 100 and pFETs to 110 to maximize mobility for both. I asked them if this is what comes after nanosheets and they said they couldn’t comment.
In my Leti interview we discussed the joint paper they did with IBM, “Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transistors”. In this work, once again focused on nanosheets/nanowires they used Transmission Electron Microscopy (TEM) imaging to image the lattice constants and measure strain. This technique allows strain to be visualized on an atomic scale.
Figure 1 illustrates the initial modeling they did of the structure that made them expect it be stressed slightly tensile.
Figure 1. Nanosheet strain modeling, image provided by Leti.
What they found when they imaged the channel was the integrated flow compressively stressed the channels from the Inter-Level-Dielectric (ILD) layers as opposed to the tensile stress they expected from modeling. You can modulate the stress from the gate stack and contacts, Leti has a lot of expertise at managing stress and with this technique they can calibrate their models. Figure 2 illustrates the results.
Figure 2. TEM image of channel strain, image provide by Leti.
The stress measurement technique used here was developed at Leti and uses a whole series of specialty techniques to make it more precise and sensitive. They also found that when you deposit an amorphous dummy gate and then recrystallize it to polysilicon, the volume reduction creates pockets and tensile strain.
The work presented at IEDM by IBM and Leti on nanosheets continues to move the technology toward volume manufacturing with improved etching, dipole-based Vt control, reduced parasitic capacitance by introducing dielectric layers under the stack, and improved understanding of stress in the nanosheet stack. Stress impacts mobility and therefore device performance and is a key parameter to optimize.
Share this post via: