Enabling the Ecosystem for True Heterogeneous 3D IC DesignsThe demand for higher performance, greater configurability, and…Read More
Why I Think Intel 3.0 Will SucceedProbably one of the most anticipated semiconductor investor…Read More
Griffin Securities’ Jay Vleeschhouwer on EDA Acquisitions and StartupsJay Vleeschhouwer, Managing Director of Software Research at…Read More
Security Coverage: Assuring Comprehensive Security in Hardware DesignAs hardware systems become increasingly complex and security…Read More
Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC3D IC was a very popular topic at…Read More
Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, with a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very cool HAPS demo… Read More
Last summer, Intel launched their 14nm, 6th Generation Core processors, code-named ‘Skylake’, alongside Microsoft’s new Windows 10 operating system. As things usually go in the enterprise world, the commercial 6th Generation of Intel’s Core vPro processors weren’t too far behind with increased security and manageability… Read More
SPIE Days 3 and 4:
Anna Lio of Intel presented EUV resists: What’s next?
Intel wants to insert EUV at 7nm but it has to be ready and economical. Critical Dimension Uniformity (CDU), Line Width Roughness (LWR) and edge placement/stochastics are all stable on 22nm, 14nm and 10nm pilot lines.… Read More
Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor platform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.
On a more technical note, he showed us a familiar survey they had completed with the… Read More
We wrote about the history of Cadence in preparation for our book “Fabless: The Transformation of the Semiconductor Industry” in 2012. EDA played a key role in enabling the fabless semiconductor revolution and Cadence was right there at the beginning. Famed EETimes editor Richard Goering helped us with the book and the Cadence… Read More
Our introduction to Flex Logix and its embedded FPGA core IP drew several comments, predominantly along the lines of a few things like this have been tried before. In this installment, we dive into the EFLX cores, the FPGA toolchain, the roadmap, and a powerful integration feature.… Read More
CNN: International, Final Report. Wednesday, December 25th, 2019 : The events that have unfolded in the last 72 hours have devastated the entire civilized world, and have left society as we know it on the brink of collapse. I’m told that our networks are now shutting down, and that the report I am about to file will be likely be the final… Read More
The internet isn’t that old if you really think about it. We’ve been working on it for decades but so far as public use, it’s only been a short span of about 20 years. In 1974, the TCIP/IP structure that we know today had it’s birth. It was not until ten years later that the first domain name system or DNS was introduced. The… Read More
It is that time again, time for the originators of the pure-play foundry business to update their top customers and partners on the latest process technology developments and schedules. More specifically, all of the TSMC FinFET processes (16nm, 10nm, 7nm, and beyond), TSMC IP portfolio (CMOS image sensor, Embedded Flash, Power… Read More
IoT products call for a higher level of system integration than ever before. Companies seeking to go to market now have a much higher bar in terms of size, power, reliability and manufacturability. The first IoT devices evolved from embedded development boards, like the groundbreaking Arduino. These were fine for prototypes … Read More
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