All Things Semiconductor!
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During 2018, Menta looked quiet if you consider communication as the main indicator of activity. In fact, the eFPGA vendor was hyper-active in developing future business and reports two main design-win. The first is with the European Processor Initiative (EPI) and Menta has announced in December 2018 that it has been selected… Read More
Writing a white paper is never tedious, and when the product or the technology is emerging, it can become fascinating. Like for this white paper I have written for Menta “How Standard Cell Based eFPGA IP are Offering Maximum Flexibility to New System-on-Chip Generation”. eFPGA technology is not really emerging, but it’s fascinating… Read More
Writing a white paper is never tedious, and when the product or the technology is emerging, it can become fascinating. Like for this white paper I have written for Menta “How Standard Cell Based eFPGA IP are Offering Maximum Flexibility to New System-on-Chip Generation”. eFPGA technology is not really emerging, but it’s fascinating… Read More
Yes, embedded FPGA is clearly an IP function, or design IP, and not a software tool or anything else. The idea to embed an FPGA block into an ASIC is not new, I remember the discussions we had in the ASIC marketing team when I was working for Atmel, back in 2000. What is new is the big interest for eFPGA in the semiconductor industry, even… Read More
Image RemovedWhat is Menta all about?
Menta was founded to add hardware-programmability within SoCs. We deliver FPGAs in hard IP form that can be readily embedded within an SoC to make certain hardware functions reconfigurable at-will, post-production. This enables customers to dynamically adapt to evolving standards, perform… Read More
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Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
Choose the Right ASIC Manufacturing Model for Your Business
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync - Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
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Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
Choose the Right ASIC Manufacturing Model for Your Business
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – “What a great idea! But I have no idea how I’d use it!”
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REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
REPLAY: Concerned about IP security threats for your SoCs?
REPLAY: Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
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[_newValues:protected] => Array
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[navigation_id] =>
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[_behaviors:protected] =>
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[_cascadeSave:protected] => Array
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[_behaviors:protected] =>
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[populated:protected] => 1
)
better_recent_comments-2
Widget_Better_Recent_Comments Instance: 2Array
(
[title] => Recent Article Comments
[number] => 10
[avatar] =>
[date] => 1
[comment] => 1
[link] => 1
[display_widget_mobile] => 1
[rw_opt] => Array
(
[widget_select] => 1
[others_front_page] => 1
[pageid_275979] => 1
)
[rw_opt_exclude] => Array
(
[pageid_274493] => 1
)
)
Widget_Better_Recent_Comments
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