WP_Term Object
    [term_id] => 65
    [name] => Menta
    [slug] => menta
    [term_group] => 0
    [term_taxonomy_id] => 65
    [taxonomy] => category
    [description] => 
    [parent] => 36
    [count] => 5
    [filter] => raw
    [cat_ID] => 65
    [category_count] => 5
    [category_description] => 
    [cat_name] => Menta
    [category_nicename] => menta
    [category_parent] => 36

CEO Interview: Vincent Markus of Menta

CEO Interview: Vincent Markus of Menta
by Daniel Nenni on 05-15-2017 at 7:00 am

Menta eFPGA LogoWhat is Menta all about?
Menta was founded to add hardware-programmability within SoCs. We deliver FPGAs in hard IP form that can be readily embedded within an SoC to make certain hardware functions reconfigurable at-will, post-production. This enables customers to dynamically adapt to evolving standards, perform security updates, or even fix hardware bugs quickly and efficiently. All of this dramatically reduces the likelihood of respins, and extends the lifecycle of SoCs.

What do you think is most unique about Menta’s technology?
Probably the most unique aspect about our technology is that we use 100% ASIC standard cells, while all of our major competitors incorporate full-custom cells to various degrees. The impact of Menta’s early decision to use 100% standard-cells is that Menta eFPGAs not only can integrate seamlessly into any customer’s EDA design flow, but more importantly, can be straightforwardly ported to literally any standard-cell based CMOS technology within just 3-4 months. When using any custom cells, this is not the case.

Using standard-cells exclusively also guarantees maximizing yield, and ensuring speed and power consumption vs. the original specification. That is because we rely upon the tested, validated simulation models of the provider supplying the standard-cell library. In contrast, because all our major competitors use full-custom cells to various extents, they are forced to rely on their own created simulation models for those custom cells, which are not able to be tested/validated to the same extent as those coming from a standard cell library provider. So in summary, what is unique about our technology is how we offer faster portability across foundries/processes, and better yield and performance-reliability vs. the original specification.

Menta has been established for quite a while, with little visibility up to now – what happened during this time?
Menta originally was founded in 2007, but the work on eFPGA started even two years before, at the LIRMM laboratory in Montpellier, France. Originally, Menta was an EDA company developing an FPGA array compiler, but then we saw more commercial opportunity in becoming a semiconductor IP company. Nevertheless, EDA is still in Menta’s DNA.

Fast-forwarding a few years, Menta then developed two eFPGA architectures, that were used within several successful French-state and European-funded projects. For example, we developed a MRAM-based FPGA for the ANR project, and Menta’s eFPGA technology was also chosen by the European Defense Agency (EDA) for a project called EDA-SoC, involving several major European defense companies.

Afterwards, Menta continued to work closely with various customers and partners to optimize our eFPGA architecture in order to meet industrial and commercial requirements. That was the point at which I decided to invest in Menta through the FJ EN private equity firm.

FJ EN’s investment enabled Menta to develop its 3[SUP]rd[/SUP] generation technology in mid-2015 and Menta had its first commercial success shortly thereafter. Finally, in 2016, Menta released its latest 4[SUP]th[/SUP] generation technology with improved density and performance. The excellent response we received from customers all over the world, caused us to significantly accelerate our business development and hiring.

As a final note, I should add that FJ EN most recently invested an additional US$ 5M in Menta.

How is Menta different from competitors?
Until our 3[SUP]rd[/SUP] generation “v3” technology was released, I would say we were really not much different from our competitors. Before our v3, we talked with multiple prospects, and while everyone found our technology interesting and potentially useful, what they really needed was for our IP to be integrateable, testable, and verifiable in the same manner as all the other standard-cell based logic IPs they were using.

So we took certain radical engineering decisions. We decided to focus not only on maximizing density and performance, but also on maximizing flexibility, testability, and verifiability of the eFPGA IP. As a result, our IPs now not only use 100% ASIC standard-cells, but they also use flops instead of SRAM, to store the eFPGA configuration. That allows Menta to deliver IP in any technology node with whatever options, based on any requested standard cell library within 3-4 months. We also offer standard scan-chain DFT with 99.8% test coverage. This latter capability required a number of unique engineering breakthroughs which we patented.

We like to say the best eFPGA IP is like a piece of wood, almost useless, without the right RTL-to-bitstream software. Our programming software, Origami Programmer, is an advanced toolsuite with a carefully crafted GUI – although TCL can also be used for command-line eFPGA programming. Origami Programmer includes synthesis, embedding the Verific parser – so there is no need to buy an external tool. With each IP, we deliver dedicated timing files so that exact timing information can be extracted and used for timing driven place & route. Origami Programmer not only outputs the bitstream file and the information for analysis, but also a simulation model with timing information to run formal verification and system level simulations. To complement Origami Programmer, we also offer an innovative eFPGA planning/specification software, Origami Designer. It allows our customers to determine the eFPGA resources they require to implement their RTL designs – not only in term of LUTs, but also DSPs and embedded SRAM.

Tell us about your IP delivery model and why you decided to provide Hard IP.
The hard IP we provide is actually a soft IP that we harden for customers as a service, based on the technology process they select. The reason Menta wants to do the hardening is that the RTL mapping process on the eFPGA can be extremely timing-critical. To add all the post-routing timing information with the desired accuracy into the Origami Programmer libraries, we found the most reliable approach would be to deliver those timing files with each IP to the customer, rather than have the customer try to generate those themselves. We felt this was the safest and most reliable approach to ensure our customers would be successful.

Are Menta eFPGA IPs silicon proven?
Yes. We have delivered our IP in STM 65nm and GLOBALFOUNDRIES 14LPP already. We taped-out a testchip in TSMC 28HPC+, and will have validation boards ready first half of 2017 to ship to prospects and customers. In addition, we are now part of GLOBALFOUNDRIES 32SOI and 14LPP IP catalog, and are working with other major foundries to integrate their offering.

What are the applications for eFPGA?
We have seen the earliest adopters in the Aerospace & Defense industry. However, we now see lot of interest in automotive, for ADAS chips, and also in various parts of IoT industry, such as using the eFPGA as a sensor hub. Menta’s eFPGA is well suited for the automotive industry, as using flops instead of SRAM to store the bitstream makes us immune from Single Event Upset (SEU) faults, and using 100% standard cells makes our IP much easier to get certified with the rest of the SoC.

In certain high-performance computing applications, eFPGA is the only solution capable of implementing parallel intensive deterministic computations with the required minimum clock-cycle latency and maximum throughput, or enabling adaptability of the system in the field within the required cost and size.

Hardware acceleration, for networking, image processing or HPC is also an emerging application.

eFPGAs can also be used to reduce time-to-market by implementing evolving algorithms directly in hardware post-production, cope with evolving standards, or even as a safety measure, to allow correcting bugs post production. Why tolerate the cost, and extra board-space of adding a small FPGA next to your ASIC, when you can have that functionality embedded within the ASIC itself? For high-volume products especially, the ROI is easy to see.

Finally, we are seeing a growing demand for programmability to implement security algorithms post production, to prevent security breaches at the production stage.

Can you share any success story with SemiWiki readers?
One of the top three US Aerospace & Defense companies late last year selected Menta to integrate an eFPGA inside their ASIC. We delivered the IP in less than four months, ahead of schedule, in GLOBALFOUNDRIES 14LPP. Everything worked the first time. As a result they decided to adopt our technology going forward and we are working with them on several new projects.

What comes next for Menta?
First, we are continuing to evolve our eFPGA architecture to accommodate even larger arrays without sacrificing performance. Second, our Origami programming software will soon allow improving eFPGA speed in the field by up to 2x, using software updates. Third, we are working on several partnerships to extend Menta’s ecosystem and provide our customers with readymade applications. Finally, Menta is building an eFPGA embedded DSP catalog to address customer needs for various applications. To accomplish all of this and support our growing customer commitments, we are hiring aggressively engineers and business developers all over the world.


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