What products are Menta offering today?
Menta is a semiconductor IP provider. We are the only proven European provider of programmable logic to be embedded inside customers’ SoCs and ASICs. This programmable logic is in the form of embedded FPGA IP. So, we offer our customers the possibility to have a small portion of their SoC as a low-power FPGA which can be programmed by them or their customers in the field. This is if you like ‘design insurance’ in a world where algorithms and requirements are changing at a much faster pace than the SoC design cycles.
So, your eFPGA IP is essentially the core fabric of an FPGA?
It is indeed tempting to summarize it like that. However, this does not accurately reflect the complete reality – and we found this out the hard way during our early years at Menta.
When we started with what was then version-1 of our eFPGA IP, we designed it with a ‘standalone FPGA mindset’. There was virtually no conceptual difference between our eFPGA IP and what you could find at that time with commercial FPGA vendors regarding their core fabric. We produced v1 and v2 of these cores, and in 2011, even an MRAM based FPGA core fabric – a world first but still with an FPGA mindset.
These offerings gave us a good market exposure and prospects started knocking at our door. However, after the excitement of the PowerPoint presentations passed, we discovered that the enthusiasm of the prospects was fading rapidly – for reasons we didn’t initially appreciate.
We experienced this the hard way with a large Japanese prospect in 2014. While we were negotiating big numbers and large volumes with their business team, their ASIC engineers raised many questions and issues regarding integration, simulation, verification, yield, final test, etc. None of those were major hurdles for us to overcome but it meant additional risk, cost, and time to integration for those engineers. We ended up losing this account, and many others thereafter, for similar reasons.
When I invested in Menta and decided to lead the company, we made a re-start to change our mindset. Our customers were SoC and ASIC designers – so we hired SoC and ASIC designers to understand their product expectations and the fundamental barriers we were experiencing in the adoption of our IP.
The cooperation of our FPGA specialists with our ASIC design specialists led to a new generation of Menta’s unique eFPGA IP – what we called v3 back in 2015 – which was born with an ASIC IP mindset and delivering a complete journey for our customers from cradle to production. And soon after we gained our first customer – a top US Aerospace & Defense company.
Moving fast forward, we are now selling our v5 IP which was released in 2018. The same principles apply but with much improved PPA with each generation.
What are those principles?
As I said, Menta eFPGA IP is designed to be integrated into an ASIC or SoC – so our primary aim is to make the complete journey of our customers from design to full production free of any friction or worry.
First, we don’t want to dictate to our customers what foundry to use, the process node, interfaces or the EDA design-flow. Of course, the earlier the decision to integrate an eFPGA IP is made, the more benefits can be gained from that integration. However, Menta eFPGA IP can still be integrated very late in the design process because of the extreme flexibility of our approach.
Let’s expand on that flexibility aspect – our eFPGA IP is based completely on standard cells, provided by the foundry, the customer or a third party – not a single custom cell is needed to use our IP. Even for the bitstream storage we use DFF for extreme portability – while most other solutions would need a custom SRAM bitcell design which limits their choice of fab or process. We don’t require any specific library, process step or metal stack for our users to deploy our IP. As a side note, DFF also makes our designs much more radiation hardened compared to SRAM base designs – an important consideration for automotive and of course space and defense.
Same thing applies regarding the interfaces to the eFPGA IP – these are all external to our blocks. Connections and communication with the IP are as simple as connecting a memory block.
We have developed and patented a standard scan chain DfT for the same reason and allow our customers to verify and simulate within their own EDA toolchain at every stage – like for any other digital IP. We realize that our eFPGA IP must not introduce any yield or reliability issues into the design of our customers.
Finally, our customers are doing ASIC design – which stands for ‘application specific’. So, we made our IP completely ‘design adaptive’ – or even ‘application adaptive’. So, it evolves with the needs of our customers. If you need a new AI algorithm, you can program it as opposed to burn it into hard gates.
I could go on for a long time with a list of requirements like verification, simulation, trust, etc.
One thing we know for sure though, is that what it takes to provide a good eFPGA IP cannot be oversimplified to physical density of look-up-tables. There are many other factors that influence the silicon area for a given RTL design like DSPs, whether memories can be integrated inside the IP itself, read/write circuitry, test circuitry, and so on. When you look at it holistically, our customers are very happy with the small silicon area trade off with the design flexibility they get.
What about Menta Software?
Our customers don’t want to introduce any complexity for their customers. If they have to buy third party software to program the chip, that is an additional degree of user friction and cost which must be avoided.
That is why, very early on, we made the correct strategic decision to develop and deliver a complete design environment for our eFPGA IP – our very own Origami programming platform which is available to all our customers. We also ensure compatibility with our customers’ existing RTL code by integrating the Verific HDL parser. It takes only a couple of hours for an FPGA engineer to master our design-flow and move their existing RTL to Menta eFPGA IP with ease. This is how our customers typically evaluate our IP and design-flow before committing to a design and has been a cornerstone of our success with a growing number of design-wins.
How long does it take and what does it cost to port a Menta eFPGA IP to a given process?
Thanks to our strategy of using only standard cells, the portability of our IP and our design-flow, it takes only between 1 to 6 months for us to deploy our eFPGA IP in a new process node. To date, our IP has been delivered on 10 different nodes across 4 different foundries – all the way from 180nm down to 6nm and getting ready to work on 5nm. As we don’t need custom cells, we do not require going through a test-chip or silicon characterization. As a result, all our deliveries have been ‘right first time’.
Our methodology has been audited several times by partners and customers and we have been qualified by GLOBALFOUNDRIES on 32SOI and 12LP and are 22FDX’celerator ecosystem members. That tells you how serious we are when it comes to quality and portability.
Why use eFPGA IP when one can buy a stand-alone FPGA?
FPGAs do a great job for those low-volume, high-value applications which require a huge number of programmable logic resources – we are speaking million of LUTs here. In the datacenter for example, AI workloads on stand-alone FPGAs are making great inroads against the GPUs.
When it comes to workloads on the Edge however, where cost and low-power are paramount considerations, stand-alone FPGAs do not make much sense – except when prototyping. In these markets, ASICs and SoCs are the real winners for the foreseeable future.
However, as I said earlier, in a world where algorithmic IP is changing at a rapid pace, it does not make sense to hardwire these into gates in an ASIC. Otherwise your chip may be still-born by the time it hits the market. This is a trend we are seeing in AI/ML, computational storage, 5G and encryption – constant change.
This is where the eFPGA shines – you allocate typically around 20% of your chip for those rapidly changing algorithms with the comfort that even if you need a different algorithm you can still program it into your ASIC – even after production. It is true that your chip will be slightly bigger (compared to hardwired gates) – but that small ‘insurance premium’ is worth it in making your chip fit-for-purpose well into the future.
We are also seeing another phenomenon among our customers – configurability. Prior to eFPGAs some customers would have 100s of different chips with slightly varying functionality. With a tiny amount of eFPGA, they can now have a single die from which they can produce 100s of different SKUs with no inventory risk. This is priceless for them.
Finally, especially in cryptography, eFPGA works as an additional level of security. If the encryption is hardwired into gates, it can always be reverse engineered. If it is only loaded into the ASIC at run-time (which you can do with eFPGA), it is much harder to reverse engineer.
In summary, we are now seeing an endless stream of new use cases which we did not envisage when we started this journey.
What is new since last time we talked?
It has been a while, so there is actually quite a lot of updates. First, we released the v5 of our IP with improved PPAs. Second, we introduced new features especially in handling memories within the IP in a completely automated and transparent way, as well as a new adaptive DSP with some patented breakthrough features – that are already in use by early adopters.
We’ll tell you more in the coming months.
Where do you see Menta eFPGA IP used?
We address four main market segments. Our early adopters have been Aerospace & Defense companies. We have multiple customers all over the world (European Defence Agency, Thales Alenia Space). Our capability to deliver trusted eFPGA IP and the various radiation hardening options we have are some of the strengths that push A&D actors to adoption.
We also have customers in computing intensive applications such as High-Performance Computing (EPI) or 5G base stations (Chongxin Beijing communication).
IoT (Edge) is another segment where our low power, small area and low cost small eFPGA IPs have a lot of success.
Automotive is an evolving segment for us where deals typically take longer but we have a strong position here and recently had the chance to discuss publicly some of the work we do with Karlsrühe Institute of Technology, Infineon and BMW.
I saw several partnerships announcement – can you tell me more?
We aim to bring our customers not only an eFPGA IP, but also all the collateral IPs and tools that will increase the value add of using Menta eFPGA IP. For this, we’ve been quietly building an exciting ecosystem.
Some partners are offering their expertise to our customers to enable applications – for example security and cryptography with Rambus and Secure-IC.
Some partners are bringing ease of use of our eFPGA like Verific for VHDL/Verilog/System Verilog parsing or Mentor Graphics Catapult to allow our customers to program our eFPGA IP in high level language such as SystemC.
We also have partners that bring SoC level applications such as eFPGA IP and CPU combination, like Andes – and others that bring technology options to our customers such as GLOBALFOUNDRIES, IMEC, Surecore or Synopsys.
Finally, we have a growing ecosystem of algorithmic IP providers who are offering their wares to our customers to enable vertical applications – from TinyML to security and cryptography applications, including those from Rambus and Secure-IC.
Watch this space!
Menta is a privately held company based in Sophia-Antipolis, France. The company provides embedded FPGA (eFPGA) technology for System on Chip (SoC), ASIC or System in Package (SiP) designs, from EDA tools to IP generation. Menta’s programmable logic architecture is based on scalable, customizable and easily programmable architecture created to provide programmability for next-generation ASIC design with the benefits of FPGA design flexibility. For more information, visit the company website at: www.menta-efpga.com