Menta is a privately held company founded in 2007 in France. The company delivers 100% third party standard-cells embedded FPGA IPs for SoC, ASIC or ASSP designs. Our technology lets you effortlessly update your silicon post-production, whether to fix a bug, implement customer-specific features, adapt to evolving standards, or enhance security. Menta IPs are delivered with the Origami toolchain to generate the bitstream from RTL, including synthesis.
Menta is backed by FJ Development EN, with an investment of more than $7M to date.
Vincent MARKUS – CEO & President of FJ Développement
Vincent has more than 15 years of experience in tech industries: 12 years in Thales as BU Manager, 3 years in Airbus as SVP Performance Management. Since 15 years, Vincent was involved in various companies’ governance and funding.
Yoan DUPRET – Managing Director & VP Business Development
Yoan has 16 years of experience in the semiconductor industry. He held various technical and managerial positions at DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor. Yoan holds a PhD from Supelec (France) and a Ingénieur degree (MSEE) from ESEO (France).
Olivier ORSINI – CFO
Olivier has 35 years of experience in international business. He served as Senior EVP of Development for South America, Africa, Middle East at EDF. Olivier also served as Senior EVP of Veolia Environnement S.A. and as the Chairman of Proactiva Medio Ambiente, S.A. Olivier is a graduate of ESCP – EAP Europe Business School.
From Menta products evaluation to eFPGA IP delivery, a Menta FAE is systematically assigned to support our customers.
Once initial discussions confirm the potential usage of Menta eFPGA IP in the customer future products, we provide our software Origami Designer and Origami Programmer to evaluate our technology. The two software allow our customers to apply their application RTL and evaluate the software capability and performances as well as the eFPGA IP PPA.
For newcomers to the eFPGA IPs world, we recommend to buy a Menta Starter Pack. Evaluation boards are also available for evaluation on silicon. Menta also provides various documents to help the evaluation phase.
eFPGA IP definition
The IP definition consists in chosing the form factor, number of eLBs, number of IOs and number and types of eCBs and eMBs. There are several ways to help performing this definition:
– at customer. There is no need to provide any application RTL to Menta.
– with Origami Designer for automatic sizing of the eFPGA
– by providing resources used on a given COT FPGA implementation to Menta
– at Menta, by providing target applications RTL.
Statement of Work (SoW)
Once the customer is ready to engage with Menta we work together and agree on a SoW. The SoW adds to the eFPGA IP definition all the deliverables details: files formats, PVT corners, verifications to run, power options, standard cells to use, PPA targets, etc.
The contracts are signed based on the SoW content.
eFPGA IP delivery
The delivery of the hardened IP is typically proposed in 3 phases:
– a container for flooplanning is delivered in a few days
– a intermediate version of the GDSII is provided for first verifications by the customer
– a final GDSII, fully verified for production, is provided
Other delivery models are possible.