Menta is a unique embedded FPGA (eFPGA) company. Their eFPGA IP is based completely on standard cells provided by the foundry, the customer or a third party – no custom cells or custom cell characterization is needed. They also don’t require any specific library, process step or metal stack. All this makes Menta’s eFPGA IP easy to embed in a standard SoC design flow. The company went through several iterations of eFPGA architectures to arrive at the current approach. The process was driven by its customers. You can learn about Menta’s journey in an interview Dan Nenni did with Menta’s CEO here. I recently had the opportunity to preview a new webinar from Menta that will be broadcast on December 15. Now, Menta is breaking new ground with eFPGA IP using adaptive DSP.
This unique adaptive DSP capability finds use in many applications, including AI, communication protocols, encryption, compression, interconnect fabrics and cybersecurity. Catherine Le Lan de Franssu, field application engineer at Menta, is the webinar presenter. She has a deep background in IC design and program management having worked at LSI Logic, Synopsys, TI and academia before joining Menta. She provides a very clear explanation of the unique and flexible DSP capability offered by Menta.
First, Catherine discusses the patented, flexible nature Menta’s eFPGA IP. The designer can define what is needed at a very granular level, including configurable lookup tables, memories from your vendor’s memory compiler, special customer-designed blocks, definition of I/O requirements (e.g., SPI, AHB, AXI, JTAG/scan chain) and a unique adaptive DSP capability. Catherine provides a lot of detail about the architecture of this DSP capability and how the designer can customize it. The configuration of registers and how pipelining can be used is also discussed.
The key goal of this adaptive DSP solution is to provide a wide range of options so the designer can choose the best hardware DSP architecture. For example, the ALU can range from 8 to 512 bits. DSP blocks can be cascaded, and the blocks can be dynamically reconfigured at each clock cycle if needed.
Catherine goes into a lot of detail about developing finite impulse response (FIR) algorithms with Menta’s adaptive FIR engine. The hardware architecture of the algorithm implementation can be tuned to hit the right performance or area target. The architecture supports from 4 to 512 taps for a FIR filter implementation. A FIR generator automatically creates the RTL code for the target implementation.
Menta’s Origami user interface coordinates all this activity. Catherine explains how Origami generates all the files needed for pre-hardening and post hardening IP verification. She also explains some of the special capabilities of the DSP that make it highly testable.
Example implementations are then described. A 24X24 complex multiplier is covered in detail, including performance metrics. A 21-tap FIR filter implementation is also detailed using a 16-bit bus. The primary goal in this case is size and Catherine shows how to use the Oragami interface to achieve the required area.
The webinar concludes with a good Q&A session that covers many more features and capabilities of Menta’s DSP. If your next design will require DSP, I highly recommend you attend this webinar to see how Menta is breaking new ground with eFPGA IP using adaptive DSP. The webinar replay can be found HERE.Share this post via: