With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device. The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.
I will talk to the EDA companies on what design challenges we can expect for the GAA process technology and what they have discovered thus far. SemiWiki will also cover the upcoming GAA related papers and announcements so stay tuned.
To start I spoke with Aveek Sarkar, VP of Engineering at Synopsys. He is a 20+ year semiconductor professional splitting his time between Sun Microsystems, ANSYS, and Synopsys. Aveek’s focus today is delivering a modern and open custom design platform that is changing the way analog and custom circuits are created.
Given that Synopsys is an IP powerhouse with hundreds of internal designers using Synopsys tools, I felt this would be a good starting point. IP is the foundation of semiconductor design and is always first to a new process node.
These questions are a follow-up to the press release Synopsys did with Samsung last month:
- Samsung and Synopsys collaboration will accelerate deployment of 3nm gate-all-around (GAA) process technology by designers of advanced applications
- AMS Design Reference Flow provides complete methodology for analog/mixed-signal design at 3nm, including documented flows for design, layout, reliability analysis and signoff
- Synopsys Custom Design Platform delivers industry-leading productivity for Samsung 3nm GAA design, including innovative features for reducing time to analog design closure
“With the Synopsys AMS Reference flow, designers can quickly deploy 3nm GAA technology for their most demanding applications, such as artificial intelligence, 5G networking, automotive, the Internet of Things and advanced data centers,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “The advanced methodologies enabled by Synopsys help our customers and internal IP developers to create analog and mixed-signal designs more efficiently.”
“In developing the 3nm GAA AMS Design Reference Flow, Samsung and Synopsys worked together to enable powerful techniques for shortening design cycles,” said Aveek Sarkar, vice president of engineering at Synopsys. “As one example, the reference flow with Synopsys includes a novel solution for early electromigration analysis, which substantially shrinks design closure time.”
What new Synopsys tool features were required in support of the Samsung 3GAA technology?
From a tool feature POV, the change from FinFET to GAA was not as disruptive as the change from Planar to FinFET. However, we are finding with each new node there is a significant amount of “methodology tuning” that needs to take place. For this, we work together with our DesignWare IP development team to develop flows that work best for each new process. In the case of 3GAA, we believe that signoff quality early analysis of electrical effects has moved from a “nice to have” to an essential feature. A lot of our collaborative work with Samsung has been focused there. This includes in-design analysis of resistance, capacitance and electromigration during layout.
What is “early” EM analysis, as mentioned in the press release?
Early EM analysis is analysis that takes place before a given block of layout is finished. In a traditional flow, the layout team will finish a block so that it can go through a normal signoff flow – running LVS and extraction and then post-layout simulation and finally EM analysis. Fixing EM issues at this stage requires a lot of rework – to reduce current density on a path, you need to make room for the new routing resources. Our flow allows you to check for EM errors with signoff engines while layout is in progress.
You are correct that analyzing EM for a net for self-heating effects requires that the underlying devices be placed first. We do include self-heating effects in our EM calculation. Early EM analysis is performed by layout designers during the interconnect process, so usually the related devices will be placed.
Fundamentally, our goal is to “shift left” electrical analysis – finding electrical issues earlier in the design cycle – while using the full accuracy of the signoff tools. This delivers good correlation with the final signoff results even without fully completed layout. Besides early analysis, we also provide EM-aware routing that generates correct-by-construction connections.
For more on the Synopsys Custom Design Platform, visit https://www.synopsys.com/custom.