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Virtual events are coming fast and furious. Even though we are sheltering there is still the need to pick and choose carefully because time really is big money inside the semiconductor design ecosystem, absolutely.
Synopsys virtual events are high on my list for three reasons:
They are very well organized and professionally done
Great customer driven content
Who knows more about design and IP than the #1 EDA and #1 IP company?
Next up is the Synopsys Digital Design Symposium on October 14. Even though I do miss the networking and great food at Synopsys live events, I really am enjoying watching these events from my La-Z-Boy command center. Not to mention the ability to hit pause and rewind for better blogging.
HPC, 5G, mobile, automotive, AI: these are the technology segments that are bringing new design challenges to ASIC and SoC designers. For the past two years, Synopsys has been hard at work delivering a continuous stream of innovative products with future-proof technologies to address ultra-low power design, exploding design sizes and signoff scenarios, functional safety, security, and yield optimization. The Digital Design Technology Symposium is an event that showcases Synopsys’ digital design solutions.
With something of interest for a broad range of market segments, drop in and see how Synopsys’ innovative solutions can help with your next design. Whether you are targeting improved power, performance and area, yield, time-to-market or all of the above, recent advances in Synopsys’ Fusion Design Platform solutions can help you meet your digital design goals. You will gain new insights from Synopsys R&D experts, users, and partners on integrated, end-to-end solutions being used to achieve industry leading QoR and productivity in key areas.
Who Should Attend?
Digital design managers/directors, and engineers working on their next SoC or ASIC. Especially those challenged by requirements in the HPC, 5G, mobile, automotive, and AI market segments. CAD managers/directors looking to integrate the latest design innovations into their in-house design flows to boost design team productivity and improve design quality. Senior level engineering management wanting to understand where Synopsys is headed and why they should invest long term in Synopsys design solutions.
Wednesday, October 14, 2020
Running with the Bulls: Synopsys Innovations to Address the Next Wave of Design Challenges
Wednesday, October 14 | 9:00 AM PDT
With semiconductors fueling much of the ”Smart Everything” revolution, EDA has been front-and-center in the spotlight as a key enabler for continuing density, performance and performance-per-watt improvements. The challenges faced by advanced node designers include timely enablement, full-flow throughput, end-to-end power optimization and multi-die integration to name a few. In addition, AI hardware accelerators are driving strong interest in domain specific architectures and the need for rapid RTL exploration with accurate power, performance and area (PPA) measurements. Looking ahead, AI/ML and Cloud open up several new innovations in the EDA space to optimize and accelerate EDA flows. With functional safety, reliability and security concerns paramount in mission-critical applications, design flows need to natively represent these careabouts without compromising design PPA goals. In his presentation, Shankar will review the latest innovations in Synopsys’ Fusion Design Platform to address these challenges and opportunities.
Cost, Differentiation and Time-to-Market: How Hyperconvergence in EDA is Helping Solve Key Business Growth Imperatives
Wednesday, October 14 | 9:25 AM PDT
To execute successfully in critical market segments such as automotive, industrial & IoT, mobile and communications infrastructure requires a laser focus on differentiation, cost and time to market. Increasing complexity as the transition is made to advanced process nodes requires a redefinition of the SoC development flow to substantially lower project cycle times and increase engineering efficiency. Parallel execution is critical to meeting 10-week cycle times and addressing the challenges faced with a 6x increase in instances per square millimeter. Many metrics of engineering efficiency need to be monitored and improved as design complexity increases and fewer engineering resources are available. These challenges are driving the need for a highly convergent, vertically integrated digital design solution that delivers predictable quality of results together with faster turnaround times. Learn more about the SoC design challenges being faced and how these are being addressed today.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.