CEO Interview with Sergiy Nesterenko of Quilter on AI PCB Layout

Sergiy Nesterenko is founder and CEO of Quilter, which builds physics-driven AI for printed circuit board (PCB) layout. He triple majored in mathematics, physics, and chemistry at UC Berkeley and worked in the electromagnetic interference and compatibility (EMI/EMC) group at SpaceX during the early Falcon 9 era before founding Quilter in 2019. Quilter is backed by Benchmark, Index Ventures, and Coatue.

Tell us about your company.

Quilter automates PCB component placement and routing using physics-driven AI. Engineers upload a complete schematic and a starter board file from their own ECAD tool and define their constraints. Within hours, Quilter returns several complete layout candidates, each with a report of which physics checks passed and failed. The engineer picks one, reviews and finishes it in their own tool, and signs it off for fabrication, the same as with any layout.

The idea came from my time at SpaceX. I was building test boards for radiation characterization, and the CAD team sitting next to me was busy with the flight computer, so I laid out my own boards. A fab could turn a board in 24 to 48 hours, and designing it took weeks.

Software solved its version of this problem with the compiler, so I started Quilter to build a compiler for circuit boards. AlphaGo Zero had shown in 2017 that reinforcement learning could learn Go from the rules alone, and we bet the same approach could learn layout from physics. Fortune 500 aerospace, defense, and consumer electronics companies are now adopting Quilter.

What problems are you solving?

The main problem is layout time. A moderately complex board can take weeks to lay out by hand, and a full computer or automotive system can take months, while firmware and validation wait on it. For semiconductor teams, the evaluation board or validation fixture can become the schedule bottleneck once silicon is ready to test. Every respin adds another round of layout, fabrication, and bring-up.

Chip place-and-route was automated decades ago, and board autorouters have existed since the 1980s. People coming from silicon often assume boards are the easier case. Standard-cell digital layout runs on a regular grid, with a preferred routing direction per layer, standard via sizes, and library cells. A PCB has much less of that structure. Traces run at any angle, components come in thousands of package types, and via rules change with the fab and the stackup.

What application areas are your strongest?

Quilter lays out digital and mixed-signal boards up to about 5,000 pins, including DDR4 and LPDDR4 memory interfaces, dense BGAs, and impedance-controlled routing.

Project Speedrun, the first computer designed by physics-driven AI, shows the upper end. Fast Company named it a finalist in the Artificial Intelligence Design category of its 2026 Innovation by Design Awards. It’s a two-board Linux computer, and we published all of it: the input files, Quilter’s raw output, and the final fabricated designs, so engineers can see what cleanup changed. Quilter placed and routed its 843 components and 5,141 pins in 27 hours of runtime. Layout services had quoted 428 hours to do it by hand. Our engineer spent 38.5 hours on cleanup, and the boards ran Linux with LPDDR4 memory, Ethernet, USB, HDMI, and graphics capable of running hardware-accelerated Chrome and games, with no respins. EMC consultant Ken Wyatt has since measured their radiated emissions in a pre-compliance bench test. From roughly 250 to 650 MHz they ran well below a board we built from NXP’s reference design files.

Teams usually start with the boards that wait longest in the layout queue: IC evaluation boards, design validation boards, test fixtures, and prototype baseboards. The best fit today is under 48 V and 10 A. Quilter routes through-hole vias only, so boards that need blind, buried, or microvias aren’t a fit yet, and neither are RF or high-voltage designs.

What keeps your customers up at night?

Most of them don’t have enough layout capacity. One layout lead told us flatly that he can’t be scaled. Behind that is a knowledge problem. One customer has forty engineers, a dozen who can do PCB design, and one person who has done nothing but high-speed layout for thirty years. Contractors add bandwidth, but they expect explicit direction, so a senior engineer ends up supervising them. When a contracted layout comes back wrong, that engineer drops other work to fix it.

What does the competitive landscape look like and how do you differentiate?

Most engineers compare us to the autorouter. One prospect, after seeing results, said it looked like “what everybody hoped an autorouter would be.”

Every major commercial PCB design tool includes one: Situs in Altium Designer, Allegro PCB Router in Cadence (originally SPECCTRA), and the routing tools in Siemens Xpedition. An autorouter covers roughly the routing step of chip place-and-route. The designer places the components and sets width, clearance, and via rules, and the router, at heart a geometric maze solver, finds paths that fit those rules.

Whether a board works depends on its physics: impedance, current capacity, return paths, and coupling between nets. A geometric router can’t see any of that, so the engineer translates every electrical requirement into a geometric rule by hand, and one missing rule can produce a board that passes design rule checks (DRC) and misses its impedance targets.

We built Quilter from first principles, starting with the physics. It places and routes together, computes trace geometry for target impedance from the customer’s actual stackup materials using Simberian’s Simbeor field solver, sizes each trace for the current its net carries, and attaches a physics rule check report to every candidate alongside DRC. The layout engine is a reinforcement learning agent trained on synthetic boards scored against physics.

ECAD vendors sell the autorouter as one feature in a suite that also covers schematic capture, libraries, simulation, and data management, and Cadence and Siemens build chip design tools too. Quilter works alongside those suites, reading and writing native Altium, Cadence Allegro, Siemens Xpedition, and KiCad files, and layout automation is the only problem we work on.

Building physics into a layout engine takes a research team. Ours includes PhDs in physics, math, computer science, and machine learning, working with engineers from SpaceX, NASA, Apple, Google, and Waymo and EDA developers from Cadence and Synopsys. In September, Eric Bogatin joined as our first Technical Fellow. Eric is a physicist by training and one of the most respected experts in signal integrity. He wrote Signal and Power Integrity: Simplified, the textbook most engineers in our field learned from, and more than a dozen other technical books. He was technical editor of Signal Integrity Journal and teaches at the University of Colorado Boulder. At Quilter, he advises our physics and engineering teams and gives feedback on the product and roadmap.

What new features and technology are you working on?

This year’s releases focus on reading the engineer’s intent from their design files. Automated ball grid array (BGA) fan-out shipped in May. Because fan-out is solved together with the rest of the board, it removes a manual prep step and dense designs route better. Calculated impedance profiles and ground net selection also shipped. Quilter now reads net-class, layer, and pair clearance rules from Altium Constraint Manager in beta, with other ECAD tools to follow. Blind and buried vias are in development and will open up more high-density interconnect (HDI) designs.

How do customers normally engage with your company?

Commercial teams start with a paid pilot on a real board from their own backlog. Each board is priced by the number of pins to route, which matches how these teams already pay for outside layout services. Quilter runs in our managed AWS cloud by default, and teams with stricter security requirements can self-host it in their own environment, including fully air-gapped. The enterprise version doesn’t use customer designs for training.

Early-stage hardware startups can apply to our startup program. Hobbyists, students, and researchers can use the free version for non-commercial work.

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