CXO Interview with Solaiman Rahim of ChipAgents

Dr. Solaiman Rahim is a multidisciplinary technology executive with over 25 years of experience driving innovation in the chip automation space at the intersection of systems, semiconductors, high-performance computing, and AI. As Chief Product Officer at ChipAgents, he leads the scaling of the Agentic and Native AI platform in close collaboration with customers. He was previously Vice President of R&D at Synopsys, where he led and scaled the Signoff, ECO and Power platform working closely with customers like Nvidia, Broadcom, Apple, and Google helping them design the world’s most advanced chips improving their time to market, PPA and productivity. Prior to Synopsys, Solaiman held senior management roles at Atrenta, where he led the Spyglass constraint and power products as part of the Spyglass platform scaling them to 100+ customers. He started his career as a formal verification engineer at Synplicity.

What brought you to ChipAgents?

Over the course of my career, I’ve worked closely with customers like NVIDIA, Broadcom, Samsung, Intel, MediaTek, and TSMC. From that vantage point, I watched demand for semiconductors and the complexity of chip design grow faster in the last few years than in the previous two decades. Die sizes, packaging complexity, and the requirements on performance, power, thermal, and area all became dramatically more demanding, driven by constrained foundry capacity, the explosion of AI workloads, and the power limits of the data center.

Two things became clear to me. First, the existing solutions, built on architectures that are decades old, could not scale to meet this complexity. Second, AI on its own could not solve these challenges either. What the industry needed was a full-stack, AI-native vertically integrated platform with its own physics-aware models: one that boosts productivity, improves PPA, and reduces cost at the same time; that can co-optimize multiple objectives almost exhaustively; and that delivers 10x faster time to market with fewer resources than traditional flows. A platform that turns every engineer at our customers into a super-architect spanning multiple domains. That is why I joined ChipAgents.

What is the biggest challenge your customer is facing?

The challenge we hear consistently from customers is that chip complexity is increasing much faster than engineering capacity. You have more custom chips, more aggressive PPA targets, increasingly complex verification requirements and much tighter schedules, but the way engineers move through the design flow is still highly fragmented. They may have excellent tools for synthesis, verification, timing, power or physical design, but a great deal of engineering effort is still spent carrying context between those tools, analyzing results and debugging manually, and deciding what to do next.

That becomes particularly painful when you get into analog flows, because the problems are interconnected. Engineers must balance gain, bandwidth, noise, linearity, stability, power, and area. Each design change can require multiple SPICE analyses. Placement, routing, matching, and parasitic resistance and capacitance influence circuit behavior. Post-layout simulation can expose failures that send engineers back to sizing or topology decisions, creating repeated design loops. Customers are looking for a way to compress those loops without sacrificing quality or signoff confidence.

Why is your approach to solving this problem unique?

Our view is that you cannot solve this simply by putting a stronger model in front of an existing workflow. Chip design is a multi-objective optimization problem, and the AI has to understand the design, the customer’s methodology, the available tools and the physical consequences of the decisions it is making.

That is what we built IC-star to do. It is our chip neural engine bringing together the customer’s engineering knowledge, agentic reasoning, model selection, tool execution and physical intelligence so those elements can be optimized together rather than independently. Instead of an engineer manually deciding which model or tool to run at every step, the system can evaluate the current design state, determine the next action, execute it, learn from the result and continue moving toward closure.

The important difference for us is that the objective is not to automate one task. It is to improve the total engineering outcome across, time to results, PPA, engineering resources and overall cost across digital and analog.

What other approaches are being used to solve this problem?

There is a lot happening across the industry right now. DA vendors are adding AI to existing tools, semiconductor companies are building internal agents, and engineers are using general-purpose models for coding, verification, and debug. Each can deliver value. The harder question is whether they can carry a design through the entire engineering flow.

Even the most powerful frontier models still struggle with that challenge. In our initial Build-A-Chip-Bench evaluation (a new AI benchmark collaborated with NVIDIA), the highest-scoring model achieved a 16.6% success rate.

Producing plausible RTL is one step; carrying a design through verification and physical implementation, while meeting real constraints, requires much more.
Internal teams can build agents tailored to their environment, but they also take on an ongoing infrastructure commitment: integrating tools, evaluating new models, maintaining workflows, and enforcing data security. For semiconductor companies, that can pull scarce engineering resources away from designing differentiated silicon.

AI on top of individual EDA tools can accelerate specific tasks. But if engineers still have to transfer context, interpret results, and coordinate the next step across tools, the broader design loop remains heavily manual.

That is also why we have taken a model-agnostic and tool-agnostic approach. The customer should be able to use the best model and the best engineering tool for a particular task rather than being locked into one stack.

What challenges will your customers face in the near future?

Trust and scalability are going to become very important as AI moves deeper into production design.

A semiconductor company’s IP extends beyond its design files to its methodologies, optimization recipes, and accumulated engineering judgment. As AI learns from that context, customers need control over where it runs, what it can access, and where that knowledge is retained. They need to build on their proprietary expertise without allowing it to leave their building.

There are also resource constraints. Different engineering workflows benefit from different models and compute resources. Some require frontier-level reasoning, while others run more efficiently on smaller, domain-specific models. Certain workloads are better suited to CPUs; others benefit from GPU acceleration. The system needs to match each task to the right model and available compute, balancing engineering accuracy, turnaround time, and cost within the customer’s infrastructure.

How has AI changed your business strategy?

AI changes the level at which we can think about semiconductor design. Historically, we built tools that automated individual steps in the design flow and then relied on engineers to connect those steps together. With agentic AI, we can start to close several parts of the flow together and optimize toward the final engineering objectives.

That is a significant change in abstraction. Instead of telling a tool exactly what operation to perform, the engineer increasingly can define the intent, the constraints and the target outcome, and the AI system determines how to get there using the appropriate models, tools and engineering knowledge.

We still have a long way to go, but that is the direction we are building toward with IC-star: moving from point automation toward an AI-native engineering system that can take more responsibility for execution while the engineer remains focused on architecture, requirements, critical tradeoffs, and signoff.

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