Fully Automating Chip Design

Fully Automating Chip Design
by Hans Bouwmeester on 05-23-2024 at 6:00 am

Figure 1
Design Productivity Gap

Twenty-five years ago, SEMATECH first alerted the world to a concern known as the design productivity gap: the observation that the ability to manufacture complex chips had started outpacing the capability of designers to create them by more than a factor of two. This concern was subsequently reiterated… Read More


CEO Interview: Issam Nofal of IROC Technologies

CEO Interview: Issam Nofal of IROC Technologies
by Daniel Nenni on 05-24-2023 at 6:00 am

Dr.Issam AL ZAHER NOUFAL (1)

Issam Nofal is the CEO of IROC Technologies and has held various positions with the company for over 23 years as Product Manager, Project Leader, and R&D Engineer. He has authored several papers on test and reliability of Integrated Circuits. He holds a PhD in Microelectronics from Grenoble INP.

What is IROC Technologies’
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Bespoke Silicon Requires Bespoke EDA

Bespoke Silicon Requires Bespoke EDA
by Michiel Ligthart on 10-26-2022 at 10:00 am

Bespoke EDA

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according… Read More


WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud

WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud
by Daniel Nenni on 09-28-2022 at 8:00 am

How to Accelerate Ansys RedHawk SC in the Cloud

 

As we all know, growing complexity of IC designs and the resulting numbers of EDA tools and design steps lead to very intricate workflows which require compute cycles that outstrip current compute capacity of most IC enterprises. The obvious question is how to efficiently leverage near infinite compute capacity in the … Read More


Calibre, Google and AMD Talk about Surge Compute at #59DAC

Calibre, Google and AMD Talk about Surge Compute at #59DAC
by Daniel Payne on 07-25-2022 at 10:00 am

Google Cloud vendor of the year min

In 2022 using the cloud for EDA tasks is a popular topic, and at DAC this year I could see a bigger presence from the cloud hardware vendors in the exhibit area, along with a growing stampede of EDA companies. Tuesday at DAC there was a luncheon with experts from Siemens EDA, Google and AMD talking about surge compute. I already knew Michael… Read More


The Semiconductor Ecosystem Explained

The Semiconductor Ecosystem Explained
by Steve Blank on 02-06-2022 at 6:00 am

TSMC Ecosystem Explained

The last year has seen a ton written about the semiconductor industry: chip shortages, the CHIPS Act, our dependence on Taiwan and TSMC, China, etc.

But despite all this talk about chips and semiconductors, few understand how the industry is structured. I’ve found the best way to understand something complicated is to diagram… Read More


CEO Update: Tuomas Hollman, Minima Processor CEO

CEO Update: Tuomas Hollman, Minima Processor CEO
by Daniel Nenni on 11-05-2021 at 6:00 am

Tuomas Hollman Minima CEO 2

Tuomas Hollman is an experienced senior executive, with proficiency that ranges from strategy to product development and business management. He began his semiconductor industry career at Texas Instruments, serving for 15 years in increasingly important roles, including general management and profit and loss responsibility… Read More


SeaScape: EDA Platform for a Distributed Future

SeaScape: EDA Platform for a Distributed Future
by Daniel Nenni on 10-14-2021 at 6:00 am

EDA Platform for a Distributed Future

The electronic design community is well aware that it faces a daunting challenge to analyze and sign off the next generation of huge multi-die 3D-IC systems. Most of today’s EDA tools require extraordinary resources in specialized computers with terabytes of RAM and hundreds of processors. Customers don’t want to keep buying… Read More


IP-XACT The Answer for IP Reuse

IP-XACT The Answer for IP Reuse
by Tom Simon on 04-09-2019 at 7:00 am

To a lawyer, the term intellectual property means just about anything intangible that has value. However, when you bring that term up in the context of semiconductor design, it means something pretty specific to most people. Yet the implied meaning of the term intellectual property (IP) within the semiconductor field has changed… Read More


The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More