Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

We all know timing closure is one of the most challenging processes in chip design. Extracting actionable insight from massive timing reports, tracing violations back to RTL, and selecting the right fix across complex PPA tradeoffs all require deep expertise. And every change can trigger hours or days of tool runs and cross-team iteration before engineers know whether the change worked. The result is a complex bottleneck in the design process. As design complexity grows, this process no longer scales. A new approach is needed.

ChipAgents will be presenting a webinar that tackles these problems in a new way.  AI experts from the company will explore how agentic AI can shift timing intelligence earlier in the design flow, helping engineers identify root causes faster, evaluate promising fixes earlier, and reduce expensive downstream iterations.  A link to register for this important event is coming. First, let’s examine some of the details of the webinar where ChipAgents shows you how to break the timing closure bottleneck with AI.

Webinar Presenters

Two AI researchers from ChipAgents are the presenters. They are:

Nikolas Belle. Before joining ChipAgents, Nikolas was a machine learning researcher at the UCSB AI Group, an AI researcher at the Barcelona Supercomputing Center and a software & machine learning engineer at Quantum Energy, Inc.

Dakota Barnes. Before joining ChipAgents, Dakota also did work at the UCSB AI Group and the Barcelona Supercomputing Center. He was also an avionics software engineer at General Atomics and a software engineer at Seek Thermal.

These two gentlemen represent the profile of next-generation chip design researchers.

Webinar Overview

Nikolas and Dakota will take you through a detailed explanation of how various AI agents are harnessed to tame the long iterations that confront many advanced chip designs. The concept of an “AI loop” is important. Think of a loop as an entity that takes actions based on feedback from the environment until a pre-defined stopping condition is met. The presenters take you through the details of several AI loops and explain how the technology has matured, what it can accomplish and how various loops interact.

LLMs are discussed first. Next, the evolution of LLMs to agents is described. After that, the addition of validation loops is discussed that help to keep agents focused for longer horizon tasks. These concepts are than applied to chip design tasks such as RTL edits, post-synthesis STA, post place & route STA, and timing closure/signoff.

Next, how these loops are assembled in the chip design process to implement workflows is described. Some of the specifics of the ChipAgents technology are used to illustrate how the process works and what significant impacts in speed and accuracy can be achieved. The diagram below illustrates the speedup opportunity at a high level.

The graphic at the top of this post shows the components of the ChipAgents solution. I have provided a high-level overview of the topics discussed during this webinar. If you are looking for ways to reduce iteration time and achieve superior results with your existing team, I highly recommend you attend this webinar.

In just over 30 minutes you will learn a lot about new approaches to chip design using innovative, highly focused, and well-integrated AI technology from ChipAgents.

To Learn More

The webinar will be presented on Tuesday, September 29 at 10AM PDT. You can reserve your spot to attend the event here. And that’s some of the details of the webinar where ChipAgents shows you how to break the timing closure bottleneck with AI.

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