Is This the Death Knell for PKI? I think so…

Is This the Death Knell for PKI? I think so…
by Bill Montgomery on 06-10-2018 at 7:00 am

It was 1976 when distinguished scholars Whitfield Diffie and Martin Hellman published the first practical method of establishing a shared secret-key over an authenticated communications channel without using a prior shared secret. The Diffie-Hellman methodology became known as Public Key Infrastructure or PKI.

That was… Read More


Is there anything in VLSI layout other than “pushing polygons”? (7)

Is there anything in VLSI layout other than “pushing polygons”? (7)
by Dan Clein on 03-08-2018 at 12:00 pm

The time is 1995 and my mandate as Layout Manager is to grow my team. I advertised everywhere but there were no experienced people in Canada that I can hire so the solution was back to training. I was the trainer a few times in Israel in MSIL but there we had a very organised material for layout, UNIX, software, etc. We had exercises, tests,… Read More


Is there anything in VLSI layout other than “pushing polygons”? (5)

Is there anything in VLSI layout other than “pushing polygons”? (5)
by Dan Clein on 01-11-2018 at 12:00 pm

Being new in Ottawa and trying to get some momentum towards automation in full custom layout I was telling industry people that I am interested to work with everybody to move this agenda forward. My Director of Engineering at that time, Peter Gillingham, took me to visit Carleton University in Ottawa. One of his professor friends,… Read More


RISC-V Business

RISC-V Business
by Tom Simon on 12-04-2017 at 7:00 am

I was at the 7[SUP]th[/SUP] RISC-V Workshop for two days this week. It was hosted by Western Digital at their headquarters in Milpitas. If you have not been following RISC-V, it is an open source Instruction Set Architecture (ISA) for processor design. The initiative started at Berkeley, and has been catching on like wildfire. … Read More


Protecting electronics around the world, SEMI insights

Protecting electronics around the world, SEMI insights
by Daniel Payne on 11-27-2017 at 12:00 pm

SEMI is a worldwide organization with local chapters like the one here in Oregon, where I attended a recent half-day presentation by several industry experts on the topic – Globalization, How it shapes the Semiconductor industry:

  • Michael Chen, Director, Mentor – A Siemens Business
  • John Brewer, CEO, Amorphyx
  • Ed
Read More

Uber is a Cancer!

Uber is a Cancer!
by Roger C. Lanctot on 09-10-2017 at 12:00 pm

Uber’s marketing and public relations afterburners are running at full blast with a new CEO, new driver rules and promises to make amends and “turn the company around” – whatever that means. If Uber is sincere about making changes it may find itself at war with its own nature.

Uber is a liar and a thief.Read More


SEMICON West – EUV Readiness Update

SEMICON West – EUV Readiness Update
by Scotten Jones on 08-11-2017 at 12:00 pm

At the imec technology forum held at SEMICON West, Martin Van Den Brink, President and CTO of ASML presented on the latest developments on EUV. I also had an opportunity to sit down with Mike Lercel, ASML Director of Strategic Marketing for an interview.… Read More


How Far Has Design Automation Brought Us?

How Far Has Design Automation Brought Us?
by Tom Simon on 04-21-2017 at 12:00 pm

It’s always a struggle explaining electronic design automation (EDA) to people who ask me what field I am in. I have come up with simple and minimal descriptions – such as “software used for designing semiconductors.” This, of course, does little to provide any useful understanding to people who are not familiar with the field.… Read More


How to nail your PPA tradeoffs

How to nail your PPA tradeoffs
by Beth Martin on 11-03-2016 at 4:00 pm

How do you ensure your design has been optimized for power, performance, and area? I posed this question to Mentor’s Group Director of Marketing, Sudhakar Jilla and product specialist Mark Le. They said that finding the PPA sweet spot is still often done by trial and error – basically serial experiments with various input parameters… Read More


Low power physical design in the age of FinFETs

Low power physical design in the age of FinFETs
by Beth Martin on 09-30-2016 at 7:00 am

Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More