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Semiconductor Expert Forum

Podcast EP34: IP Management for Early Stage Semiconductor Companies

Podcast EP34: IP Management for Early Stage Semiconductor Companies
by Daniel Nenni on 08-20-2021 at 10:00 am
Categories: EDA, Perforce

Dan and Mike are joined by Michael Munsey, senior vice president of marketing, business development and corporate strategy at Perforce. Michael discusses the unique IP management requirements of early stage semiconductor companies and how to address these requirements. The risks associated with a sub-optimal approach are… Read More

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Have STA and SPICE Run Out of Steam for Clock Analysis?

Have STA and SPICE Run Out of Steam for Clock Analysis?
by Tom Simon on 08-20-2021 at 6:00 am
Categories: Ansys, Inc., EDA
1 Comment

Ansys clock jitter analysis

At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More

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Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target

Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target
by Mike Gianfagna on 08-19-2021 at 10:00 am
Categories: Aion Silicon, Semiconductor Services

Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target

Designing an ASIC is little bit like trying to hit the bullseye, in the dark. I’ve spent several decades in the ASIC business I can tell you this is what it’s like from first-hand experience. When the design team sets out to build a custom chip to make their product better, faster, more robust, etc. (pick the words you like), there is … Read More

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Package Pin-less PLLs Benefit Overall Chip PPA

Package Pin-less PLLs Benefit Overall Chip PPA
by Tom Simon on 08-19-2021 at 6:00 am
Categories: Analog Bits, IP

Pin less PLLs from Analog Bits

SOCs designed on advanced FinFET nodes like 7, 5 and 3nm call for silicon-validated physical analog IP for many critical functions. Analog blocks have always been node and process specific and their development has always been a challenge for SOC teams. Fortunately, there are well established and endorsed analog IP companies… Read More

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Semiconductor Growth to Continue in 2022

Semiconductor Growth to Continue in 2022
by Bill Jewell on 08-18-2021 at 2:00 pm
Categories: Foundries
3 Comments

Aug 2021 comp

The semiconductor market showed powerful growth in 2Q 2021, up 8.3% from 1Q 2021 and up 29% from a year earlier, according to WSTS. Most major semiconductor companies experienced substantial revenue growth in the quarter. The memory companies were especially strong, with 2Q 2021 versus 1Q 2021 revenue (in local currency) up 19.6%… Read More

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TSMC Wafer Wars! Intel versus Apple!

TSMC Wafer Wars! Intel versus Apple!
by Daniel Nenni on 08-18-2021 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
8 Comments

Intel TSMC SemiWiki

The big fake news last week came from a report out of China stating that TSMC won a big Intel order for 3nm wafers. We have been talking about this for some time on SemiWiki so this is nothing new. Unfortunately, the article mentioned wafer and delivery date estimates that are unconfirmed and from what I know, completely out of line. … Read More

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Controlling the Automotive Network – CAN and TSN Update

Controlling the Automotive Network – CAN and TSN Update
by Bernard Murphy on 08-18-2021 at 6:00 am
Categories: Automotive, Avery Design Systems, IP

automotive networks

Cars are hotbeds of systems innovation. I’ve been fortunate to be asked to write about many of these areas, from the MEMS underlying sensors to ISPs and radars, intelligent imaging and sensor fusion. And many aspects of design for safety within the SoCs around a car. But I haven’t written much about the networks connecting these … Read More

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Flex Logix and Socionext are Revolutionizing 5G Platform Design

Flex Logix and Socionext are Revolutionizing 5G Platform Design
by Mike Gianfagna on 08-17-2021 at 10:00 am
Categories: 5G, eFPGA, Flex Logix

Flex Logix and Socionext are Revolutionizing 5G Platform Design

The world is buzzing with 5G deployment news. It seems the entire planet anxiously awaits the step function improvement in bandwidth and latency promised by this new technology. When there is additional deployment, it’s news. When there are new chipsets and devices supporting the standard it’s news. But when there is a fundamental… Read More

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How Hyperscalers Are Changing the Ethernet Landscape

How Hyperscalers Are Changing the Ethernet Landscape
by Synopsys on 08-17-2021 at 6:00 am
Categories: EDA, Synopsys
1 Comment

How Hyperscalers Are Changing the Ethernet Landscape

It’s all about bandwidth these days – fueling hyperscale data centers that support high-performance and cloud computing applications. It’s what enables you to stream a movie on your smart TV while your roommate plays an online game with friends located in different parts of the country. It’s what makes big data analytics run swiftly… Read More

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You Get What You Measure – How to Design Impossible SoCs with Perforce

You Get What You Measure – How to Design Impossible SoCs with Perforce
by Mike Gianfagna on 08-16-2021 at 10:00 am
Categories: EDA, Perforce

You Get What You Measure – How to Design Impossible SoCs with Perforce

We all know that a trusted, reliable, and well-integrated design flow is critical to successful advanced SoC design. So is proven, robust IP. While these elements are necessary for success, they are not, by themselves, sufficient. There are other aspects to consider – measurement, tracking and coordination. We’ve all heard … Read More