Applying QED to Hardware Accelerator Verification. Innovation in VerificationQED (Quick Error Detection) can be a powerful…Read More
When Software Outruns Silicon: Hardware-Assisted Test Generation to the RescueFor the past decade, the semiconductor industry has…Read More
From Tokens to Infrastructure: Why Compute, Memory, and Power Will Determine the Future of AIBased on Dylan Patel’s SEMI Industry Strategy Symposium…Read More
Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?Intel’s 18A process technology has become one of…Read More
WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA WorkloadsIn this webinar, Google Cloud and NetApp explore…Read More
Always in motion is the future. ~Yoda
For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More
The ASIC business is getting more and more complicated. The ability to produce innovative die at a competitive price to solve increasingly complex problems just isn’t enough. The technology required to package that die is now front and center.
Here, at the junction of advanced design, process technology and state-of-the art … Read More
Next week there are two Apache, a subsidiary of Ansys, events. At DesignCon there are a couple of workshops on chip-package-system (CPS). In addition to Apache themselves, each of the two workshops has a number of representatives of leading edge companies doing semiconductor design. I already blogged about this in more detail… Read More
I have bloggedbefore Christmas about the Arteris-Sonics war, initiated by Sonics, claiming that Arteris NoC IP product was infringing Sonics patent. We had shown in this post that the architecture of Sonics interconnects IP product was not only older but also different from Arteris’ NoC architecture: the products launched … Read More
For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More
For the greater good of the semiconductor ecosystem, I have agreed to Co-Chair the 2012 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), the “Premier International Gathering for Commercial and Academic Reconfigurable Computing Application Developers”, July 16-19, 2012,… Read More
Most IC designers I talk to really enjoy the creative process of developing a new SoC design, debugging it, then watching it go into production. They don’t really like spending time learning how to make their EDA tools work together in an optimal IC design flow where they may have a dozen tools each with dozens of options. Fortunately… Read More
Looking at the huge gap between the revenue of semiconductor design and manufacturing (~$300B) and that of EDA tools, services and silicon IP combined (~6B) inspired me to look more deeply into the overall arena of semiconductors in today’s context and possibly decipher some trends which should emerge in near future. Although… Read More
Well it looks like everyone (including me) was way too conservative about Apple’s iPhone sales last quarter. Analysts were expecting Apple to sell 30M iPhones and 13M iPads. In fact they sold 37M iPhones, almost a quarter more than expected, and over 15M iPads. In fact Apple sold more iPads than HP, the largest PC manufacturer,… Read More
Apple’s blowout earnings for the quarter that just ended has huge ramifications for the entire semiconductor industry as suppliers align much closer to them or figure out how to minimize the damage that is to come through the rest of 2012. The immediate implication is that Wall St. will likely toss to the sidelines any semiconductor… Read More
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