How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROIAs computing expands from data centers to edge…Read More
Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V CoresAkeana Inc. announced a key milestone in the…Read More
An AI-Native Architecture That Eliminates GPU InefficienciesA recent analysis highlighted by MIT Technology Review…Read More
Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon SecurityIn a significant advancement for the semiconductor industry,…Read More
Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic EngineeringAt the 2026 Chiplet Summit, Synopsys presented a…Read More
Next Tuesday and Wednesday, March 13-14th, is CDNLive in Silicon Valley at the DoubleTree Hotel (which I see we are now meant to call DoubleTree by Hilton, although I still have to think twice not to call it the Red Lion, the group whose CFO at one point was Ray Bingham who was CFO and then CEO of Cadence. Trivia fact for the day).
CDNlive… Read More
There is an interview in the San Jose Mercury News with Kathryn Kranen, Jasper’s CEO. Of course the Mercury is a general newspaper and can’t expect most of its readership to have a clue what EDA is, never mind formal verification. It’s a similar problem to the one we all have when we try and explain to our families… Read More
I had no idea that there was a clock domain crossing (CDC) linkedIn group but indeed there is. Richard Brabant has set up a survey to see which tools people are using.
The graph is somewhat confusing since, for example, Cadence Conformal is currently at zero but has a significant looking bar. But far and away the market leader (in this… Read More
Designing custom IP blocks is a challenge at the transistor-level and I wanted to learn what the recommended methodology and EDA tool flow was at Synopsys. They have a webinar that you can register for and it takes 30 minutes to learn what they have to say, or you can read a White Paper. If you cannot spare that much time, then my summary… Read More
I have recently blogged about Synopsys offensive in the Verification IP market. Did Synopsys again launched a new product, or announced a new acquisition? This would be a serious topic to blog, but today’s blog is closer to gaming than market analysis. Sometimes it’s good to have fun, even if the topic is serious! In fact, Synopsys… Read More
Last week I had an interesting meeting with GLOBALFOUNDRIES executives Kevin Meyer and Mojy Chian. It certainly seems that GFI has turned a corner! I will be in Dresden next week for DATE 2012 and will also visit the GFI Fab there. 28nm and 20nm are on track so expect an aggressive implementation plan from GFI this year.… Read More
As I have been watching the developments in EDA and Semiconductor industry, it is apparent that we remain fragmented unless pushed to adopt a common standard mostly due to business reasons. Foundries are dictating on the rules to be followed by designs, thereby EDA tools incorporating them. Also, design companies needed to work… Read More
Now that the dominant approach to building an SoC is to get IP from a number of sources and assemble it into a chip, the issue of IP quality is more and more critical. A chip won’t work if the IP doesn’t work, but it is quite difficult to verify this because the SoC design team is not intimately familiar with the IP blocks since… Read More
Last May, Atrenta and TSMC announced the Soft-IP Alliance Program which uses SpyGlass and a subset of its GuideWare reference methodology to implement TSMC’s IP quality assessment program. TSMC requires all soft-IP providers to reach a minimum level of completeness before their IP is listed on TSMC online. Since TSMC … Read More
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A Detailed History of Samsung Semiconductor