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From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators
by Daniel Nenni on 03-05-2026 at 8:00 am

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Ceva, Inc., a leading provider of silicon and software IP for the Smart Edge, has unveiled PentaG-NTN™, its groundbreaking 5G Advanced modem IP subsystem tailored for satellite user terminals in Low Earth Orbit (LEO) and Medium Earth Orbit (MEO) constellations. Announced at Mobile World Congress 2026 in Barcelona on March 3,… Read More


Siemens Reveals Agentic Questa

Siemens Reveals Agentic Questa
by Bernard Murphy on 03-05-2026 at 6:00 am

Questa Agentic

There’s no denying that verification now leads the field in agentic AI announcements, accelerating the trend around this significant contribution to design automation. Siemens have just announced their Questa One Agentic Toolkit, their response to this trend, building on the core Questa One platform. Questa One provides … Read More


Functional Safety Analysis of Electronic Systems

Functional Safety Analysis of Electronic Systems
by Daniel Payne on 03-04-2026 at 10:00 am

hyperlynx ams

Safety engineers, hardware designers and reliability specialists in safety-critical industries like automotive, aerospace, medical device and industrial automation use FMEDA (Failure Modes, Effects and Diagnostic Analysis). ISO 26262 compliance for ADAS, braking systems and ECUs require FMEDA in the automotive sector.… Read More


RVA23 Ends Speculation’s Monopoly in RISC-V CPUs

RVA23 Ends Speculation’s Monopoly in RISC-V CPUs
by Jonah McLeod on 03-04-2026 at 8:00 am

RVA23 Image

RVA23 marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores.… Read More


Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems
by Kalar Rajendiran on 03-03-2026 at 10:00 am

UCIe bump planning in 3DIC Compiler Platform

The first article in this series examined how feasibility exploration (hyperlink to SemiWiki first article) enables architects to evaluate multi-die system configurations while minimizing early design risk. Once architectural decisions are validated, designers must translate conceptual connectivity requirements … Read More


CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety

CHERI: Hardware-Enforced Capability Architecture for Systematic Memory Safety
by Daniel Nenni on 03-03-2026 at 8:00 am

CHERI Technology Overview 2026

The rapid escalation of cyberattacks over the past two decades has exposed a fundamental weakness at the core of modern computing systems: the lack of memory safety. Industry data consistently shows that the majority of critical software vulnerabilities stem from memory corruption issues such as buffer overflows, use-after-free… Read More


WEBINAR: Two-Part Series on RF Power Amplifier Design

WEBINAR: Two-Part Series on RF Power Amplifier Design
by Don Dingee on 03-03-2026 at 6:00 am

VNA inspired simulated load pull setup for RF power amplifier design

At lower frequencies with simpler modulation, RF power amplifier (PA) designers could safely concentrate on a few primary metrics – like gain and bandwidth – and rely on relaxed margins to ensure proper operation in a range of conditions. Today’s advanced RF PA design is a different story. mmWave and sub-THz frequencies introduce… Read More


Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain

Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
by Admin on 03-02-2026 at 10:00 am

RISC V 3PIP CWE Workflow BR 022626

by Jagadish Nayak

RISC-V adoption continues to accelerate across commercial and government microelectronics programs. Whether open-source or commercially licensed, most RISC-V processor cores are integrated as third-party IP (3PIP), potentially introducing supply chain security challenges that demand structured,… Read More


Apple’s iPhone 17 Series 5G mmWave Antenna Module Revealed to be Powered by Soitec FD-SOI Substrates

Apple’s iPhone 17 Series 5G mmWave Antenna Module Revealed to be Powered by Soitec FD-SOI Substrates
by Daniel Nenni on 03-02-2026 at 8:00 am

Qualcomm’s QTM565 mmWave Antenna Module

Recent independent teardown and technical analyses have confirmed that the 5G mmWave antenna module powering Apple’s latest iPhone 17 lineup relies on advanced SOITEC based Fully Depleted Silicon-On-Insulator (FD-SOI) substrate technology. The discovery highlights a significant architectural shift in high-frequency… Read More