Block RAM integration for an Embedded FPGA

The upcoming Design Automation Conference in San Francisco includes a very interesting session –“Has the Time for Embedded FPGA Come at Last?” Periodically, I’ve been having coffee with the team at Flex Logix, to get their perspective on this very question – specifically, to learn about the key features that customers are seeking to accelerate eFPGA IP adoption. At our recent kaffeeklatsch, Geoff Tate, CEO, and Cheng Wang, Senior VP Engineering, talked about a critical requirement that their customers have.

Geoff said,“Many of our customers are current users of commodity FPGA modules seeking to transfer existing designs into eFPGA technology, to leverage the PPA and cost benefits of SoC integration. One of the constituent elements of these designs is the use of the “Block RAM” memory incorporated into the commercial FPGA part. We had to develop an effective, incremental method to incorporate comparable internal RAM capabilities within the embedded FPGA IP. Flexibility is paramount, as well – we need to be able to accommodate different array types and configurations, with a minimal amount of our engineering team resources.”

Figure 1. Illustration of the integration of memory array blocks in a vertical channel between eFPGA tiles.

Cheng added, “Recall that the fundamental building block of our IP is the tile. eFPGA designers apply our tools to configure their IP as an array of tiles.” (Here’s a link to a previous article.)

“The edge of the tile is developed to provide an appropriate mix of inter-tile connections, balanced clock tree buffering, and the drivers and receivers for primary I/O ports on perimeter tile edges. To accommodate the customer need for memory arrays, we’ve developed an internal methodology to space the normally abutting tiles and introduce banks of memory blocks.”, Cheng continued.

The unused drivers/receivers at the interior tile edges provide the necessary interface circuits to the memory block, driving the loads of the memory inputs and interfacing the memory outputs back to the eFPGA switch fabric. A portion of the clock buffering and balancing resources at each tile edge is directed to the clock inputs of the array.

“Are the internal eFPGA memory blocks constrained to match the Block RAM in a commercial part?”, I asked.

“Not at all.”, Geoff replied. “We have customers interested in a wide variety of array size and port configurations. And, they are extremely cost-conscious. For example, they do not want the overhead of a general, dual-port memory configuration for their single-port designs.”

“To support this flexibility, we had to enhance our compiler.”, Cheng added. “The netlist output of Synplify is targeted toward the Block RAM resources of the commercial parts. When reading that netlist into the eFLX compiler, we re-map and optimize the Block RAM instances into the specific memory block configuration of the eFPGA.”

“What are the signal interconnect design requirements over the memory block?”, I asked.

Cheng answered, “We anticipate the memory arrays in the rows and columns between tiles will be fully blocked up through M4. Our inter-tile connections to the switch fabric are above M4. The power grid design readily extends to support the memory block, as well.”

Figure 2. A recent testsite design tapeout with embedded array blocks between tiles.

Cheng summarized the discussion well. “We have developed a methodology to allow our engineering team to develop an eFPGA design addressing customer requirements for memory blocks, with an incremental amount of internal resources. We are leveraging the tile-based architecture and the tile edge circuitry to simplify the integration task. Our engineering team does the electrical analysis of the final implementation. The customer utilizes the existing eFLX compiler, reading in the additional SDF timing library released for the internal memory array blocks.”

Geoff added, “This interface and implementation method would support the integration of a general macro between tiles, within the overall LUT and switch architecture of the eFGPA.”

So, back to the DAC session question – has the time for eFPGA IP arrived? If designers have the flexibility to quickly and cost-effectively integrate additional hard IP within the programmable logic of the eFPGA, without significant changes to the design flow, that’s pretty significant.

I’m looking forward to the DAC session, to see if others concur that the time is indeed here.

For more information on the Flex Logix RAMLinx design implementation for embedded memory blocks, please follow this link.

-chipguy