Reconfigurable redefined with embedded FPGA core IP

On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety of applications and modified very quickly.

Soon, many of these applications leveraged the DSP capability of FPGAs. Some experimented with various topologies such as systolic arrays, and several interconnect strategies emerged including fixed crossbars and high pin count programmable interconnect chips. To tackle bigger data flow problems, FPGAs got bigger and faster, with more I/O pins and more look-up tables (LUTs) and advanced clocking and other architectural improvements.

While FPGAs grew, board and system computing shrank. Functions that used to require several boards shrank to a single-board computer, then shrank again to system-on-chip. FPGAs responded with their own SoC strategy, large enough to hold one or more processor cores interconnected with programmable logic. Reconfigurable computing is now often self-contained in a single high performance chip – in some cases, a very expensive one.

If that FPGA-based SoC configuration happens to fit in terms of price, performance, size, and development tools and schedule, it’s wonderful. When unit volumes grow over tens of thousands, cost advantage typically belongs to a purpose-built SoC, tuned for specific requirements and assembled from third-party and internally developed IP. However, what if some reconfigurable logic is still needed at points inside an SoC or microcontroller?

Nearly 30 years after the FPGA debuted, Flex Logix was formed in March 2014 based on programmable logic technology described in a ISSCC paper from UCLA alumni Cheng Wang and Fang-Li Yuan. CEO Geoff Tate (of Rambus fame) set a course away from competing with FPGA companies, instead adopting an IP strategy and aiming to embed reconfigurability in high-volume SoCs for mobile, IoT, wearable, server, and other applications. Flex Logix begins 2016 with 1 patent issued and 6 more applications pending, a recent $7.4M round of Series A1 financing, a new VP of silicon engineering in Abhijit Abhyankar, and a new VP of sales in Andy Jaros.

Doesn’t an IP strategy run right into the likes of CEVA? It depends. CEVA DSP IP is C-programmable, optimized for low power but still more flexible DSP aimed at LTE, embedded vision, and other applications, and they are continually pushing the size and power envelope lower. What Flex Logix is doing with EFLX is very targeted hardware acceleration blocks woven into specific points of the SoC, with RTL reconfigurability. The Flex Logix EFLX IP offers customers control over logic implementation and interfacing, rather than just its programming.

A bigger issue is why an SoC team would need reconfigurability if they are allegedly developing a chip to specific requirements. EFLX cores offer roadmap control in areas where standards are still in flux or altogether in doubt of adoption, or where customer or regional requirements vary – pain points where if the guess is wrong, roadmap failures follow.

Perhaps the requirement is for a reconfigurable radio block for IoT devices or sensor hubs, or a digital front end for 4G or 5G, or an encryption engine, or SSD pre-processing for Apache Spark clusters, or a real-time analytics acceleration block in a server chip. Instead of locking in an SoC design with hard wired logic, or trapping something deeply proprietary for a specific customer preventing sales to other customers, using EFLX cores allows a single SoC design to adapt to multiple requirements quickly using point RTL reconfigurability. EFLX cores also allow field reconfiguration, an essential need for long lifecycle devices.

EFLX cores are RAM-based, programmed from RTL converted into a stream of configuration bits. The current technology is the EFLX-2.5K core, available in TSMC 28nm HPM/C and packing 2.5K LUTs as the name implies. It only requires 6 metal layers instead of the traditional 10 or more in conventional mesh FPGAs, and offers 1.8x higher logic density thanks to optimized interconnect.

Architecturally, core tiles can be combined into arrays (square, MxN, or L-shaped). For the EFLX-2.5K, up to a 7×7 array is feasible for a total of 122.5K LUTs. This hearkens back to the systolic arrays with multiple FPGAs of yesteryear, but minus the nasty external chip-to-chip interconnect problems. An EFLX tile array can implement an optimized data flow DSP pipeline, or multiple EFLX tiles could be scattered across functional blocks in an SoC – designers have flexibility.

Now that we understand the why behind the Flex Logix strategy and this new definition of a reconfigurable SoC, we’ll take a look at the how next. We’ll share more on the EFLX cores and roadmap, the FPGA toolchain, and some of the interfacing and debug techniques. If you’d like to read ahead for discussion, visit the Flex Logix website.

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