Using eFPGA to Dynamically Adapt to Changing Workloads

In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been categorized into eight different subject matter tracks. The tracks were Advanced Packaging Solution and Chiplet, Analog and Memory Blocks, Design and Verification, Interface IP, Security Solutions, Automotive IP and SoC, Video IP and High-Performance Computing.

One of the presentations under the high-performance computing (HPC) track was by Andy Jaros, VP IP Sales and Marketing at Flex Logix. The talk was titled “Using eFPGA to Dynamically Adapt to Changing Workloads.”

As we know, current FPGA company landscape is very different compared to even a few years ago. Altera was acquired by Intel a few years ago. Xilinx is going through the process of merging with Advanced Micro Devices (AMD). Many of the FPGA startups of yester years are no longer around. At the same time, there are some new companies whose differentiated technologies are experiencing market adoption success. But embedded FPGA in itself is not a new product offering. And dynamically adapting to workloads is not a new concept.

So, I listened to Andy’s talk with the goal of understanding why the market would want the solution more, this time around. This blog includes a summary of what I gathered from Andy’s talk. For complete details, please register and listen to Andy’s presentation.

Flex Logix has an embedded FPGA (eFPGA) IP business unit and an Edge Inferencing Solutions co-processor chips business unit. It has more than a dozen working-silicon chips using eFPGA, an almost equal number of chips in design and an additional two dozen chips in the pipeline. It recently closed a $55M Series D funding round. And it generates strong profits from its eFPGA IP business.

Right at the outset Andy acknowledges that dynamic reconfigurability is not new. The concept has been pursued since the late 1990s. But it didn’t take off then for a number of reasons.  In a nutshell, the concept was ahead of its time. Refer to Figure 1.

Figure 1:

Fast forward to today, market has changed a lot. Chip development costs a lot more and takes much longer than it did 10 to 20 years ago. Accelerators are drivers of next generation performance, not process nodes. Edge computing applications are driving the need for handling dynamic workloads. These applications have to work on instant data and make decisions in real time at the user end level. As a result, more throughput/$ is more critical than raw throughput. This is where dynamically adapting to workloads becomes attractive and rapid reconfigurability gets the job done.

Andy uses their InferX X1 chip implementing a neural network model to demonstrate dynamic reconfigurability concept in action. Refer to Figure 2.

Figure 2:

It is good idea to understand what is driving dynamic workload variations. This will highlight the value of reconfigurability and the importance of very fast reconfiguration times.

Many applications these days leverage artificial intelligence (AI) techniques in their implementations. AI techniques use neural network models to capture complex non-linear relationships and involve multiple layers of parallel computations between the input and output stages. Each layer may necessitate more or less computations to perform relative to the amount of memory that layer requires. This causes dynamically varying workloads that need to be executed in real time.

InferX X1 is able to reconfigure the resources into optimized hardware accelerators for each layer of the model as that layer is executed, reconfiguring in 4 microsecs between each layer. That’s incredible.  Andy talks about three use cases for applicability of eFPGA dynamic reconfigurability that can be supported today and says faster InferX type of implementation can be supported with EFLX.

Andy explains the software development flow for implementing reconfigurability using eFPGA cores and EFLX compiler. In essence, Flex Logix’s eFPGA platform makes it easy to implement reconfigurable hardware accelerators and integrate into a customer’s chips. Key workloads can be expected to execute 10-100x faster compared to general purpose processors.

He wraps up his presentation with availability status of Flex Logix’s silicon proven EFLX cores in different process nodes ranging from 40nm down to 7nm in foundries including TSMC and Global Foundries.

If you find this interesting, I recommend you listen to Andy’s entire talk and then discuss with Flex Logix for ways to leverage their product offerings for a great solution to your customer base.